On-chip upscaling and downscaling in a camera architecture

• US 9,818,169 B2
• Filed: 05/26/2017
• Issued: 11/14/2017
• Est. Priority Date: 10/01/2013
• Status: Expired due to Fees

• Current Assignee: GoPro, Inc.
• Original Assignee: GoPro, Inc.
• Inventors: Campbell, Scott Patrick, Mobbs, Paul, Adsumilli, Balineedu Chowdary, Chawla, Sumit
• Primary Examiner(s): LAM, HUNG H
• Application Number:
  US15/606,721
• Publication Number:
  US 20170262956A1
• Time in Patent Office: 172 Days
• Field of Search: 3482181, 3482221, 348294, 34833302
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 3/4015 Image demosaicing, e.g. colour filter arrays [CFA] or Bayer patterns
• CPC Class Codes: H04N 1/6019 using look-up tables H04N1/6025 takes precedence
• CPC Class Codes: H04N 1/6027 Correction or control of colour gradation or colour contrast H04N1/6058 takes precedence
• CPC Class Codes: H04N 19/102 characterised by the element, parameter or selection affected or controlled by the adaptive coding
• CPC Class Codes: H04N 19/12 Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
• CPC Class Codes: H04N 19/132 Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
• CPC Class Codes: H04N 19/156 Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
• CPC Class Codes: H04N 19/164 Feedback from the receiver or from the transmission channel
• CPC Class Codes: H04N 19/172 the region being a picture, frame or field
• CPC Class Codes: H04N 19/186 the unit being a colour or a chrominance component
• CPC Class Codes: H04N 19/1883 the unit relating to sub-band structure, e.g. hierarchical level, directional tree, e.g. low-high [LH], high-low [HL], high-high [HH]
• CPC Class Codes: H04N 19/33 in the spatial domain
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/517 by encoding
• CPC Class Codes: H04N 19/63 using sub-band based transform, e.g. wavelets
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 23/13 with multiple sensors
• CPC Class Codes: H04N 23/60 : Control of cameras or camera modules
• CPC Class Codes: H04N 23/62 : Control of parameters via user interfaces
• CPC Class Codes: H04N 23/64 : Computer-aided capture of images, e.g. transfer from script file into camera, check of taken image quality, advice or proposal for image composition or decision on when to take image
• CPC Class Codes: H04N 23/667 : Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes
• CPC Class Codes: H04N 23/6811 : based on the image signal
• CPC Class Codes: H04N 23/683 : performed by a processor, e.g. controlling the readout of an image memory
• CPC Class Codes: H04N 23/69 : Control of means for changing angle of the field of view, e.g. optical zoom objectives or electronic zooming
• CPC Class Codes: H04N 23/73 : by influencing the exposure time
• CPC Class Codes: H04N 23/80 : Camera processing pipelines; Components thereof
• CPC Class Codes: H04N 23/843 : Demosaicing, e.g. interpolating colour pixel values
• CPC Class Codes: H04N 23/88 : for colour balance, e.g. white-balance circuits or colour temperature control
• CPC Class Codes: H04N 23/90 : Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums
• CPC Class Codes: H04N 23/951 : by using two or more images to influence resolution, frame rate or aspect ratio
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 9/8042 : involving data reduction

Abstract

An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.

Claims

1. A camera system, comprising:

an image sensor chip configured to produce image data representative of light incident upon the image sensor chip;

an accelerator chip comprising;

a decimator configured to decimate the image data into a plurality of image sub-band components;

a downscale engine configured to downscale the image data using one or more of the image sub-band components; and

an upscale engine configured to upscale the image data using one or more of the image sub-band components; and

an image signal processor chip configured to process image data outputted by the image sensor chip or the accelerator chip and to output the processed image data.

2. The camera system of claim 1, wherein the accelerator chip further comprises an H.264 engine configured to decode image sub-band components encoded as H.264 video.

3. The camera system of claim 2, wherein upscaling the image data comprises decoding the one or more of the image sub-band components using the H.264 engine.

4. The camera system of claim 1, wherein the accelerator chip further comprises an VC-5 engine configured to decode image sub-band components encoded as VC-5 video.

5. The camera system of claim 4, wherein upscaling the image data comprises decoding the one or more of the image sub-band components using the VC-5 engine.

6. The camera system of claim 1, wherein the downscale engine is configured to downscale the image data by outputting a low/low image sub-band component.

7. The camera system of claim 1, wherein the upscale engine is configured to upscale the one or more image sub-band components by decoding a first image sub-band component using a first decoding algorithm, decoding a second image sub-band component using a second decoding algorithm, and combining the decoded first image sub-band component and the decoded second image sub-band component.

8. A camera system, comprising:

an image sensor chip configured to produce image data representative of light incident upon the image sensor chip; and

an image signal processor chip comprising;

a decimator configured to decimate the image data into a plurality of image sub-band components;

a downscale engine configured to downscale the image data using one or more of the image sub-band components;

an upscale engine configured to upscale the image data using one or more of the image sub-band components;

an encoder configured to encode one or more of the image data, the downscaled image data, and the upscaled image data to produce encoded image data; and

and output configured to output the encoded image data.

9. The camera system of claim 8, wherein the image signal processor chip further comprises an H.264 engine configured to decode image sub-band components encoded as H.264 video.

10. The camera system of claim 9, wherein upscaling the image data comprises decoding the one or more of the image sub-band components using the H.264 engine.

11. The camera system of claim 8, wherein the image signal processor chip further comprises an VC-5 engine configured to decode image sub-band components encoded as VC-5 video.

12. The camera system of claim 11, wherein upscaling the image data comprises decoding the one or more of the image sub-band components using the VC-5 engine.

13. The camera system of claim 8, wherein the downscale engine is configured to downscale the image data by outputting a low/low image sub-band component.

14. The camera system of claim 8, wherein the upscale engine is configured to upscale the one or more image sub-band components by decoding a first image sub-band component using a first decoding algorithm, decoding a second image sub-band component using a second decoding algorithm, and combining the decoded first image sub-band component and the decoded second image sub-band component.

15. An image signal processor chip comprising:

an input configured to receive image data captured by an image sensor chip representative of light incident upon the image sensor chip;

a decimator configured to decimate the image data into a plurality of image sub-band components;

a downscale engine configured to downscale the image data using one or more of the image sub-band components;

an upscale engine configured to upscale the image data using one or more of the image sub-band components;

an encoder configured to encode one or more of the image data, the downscaled image data, and the upscaled image data to produce encoded image data; and

an output configured to output the encoded image data.

16. The image signal processor chip of claim 15, wherein the image signal processor chip further comprises an H.264 engine configured to decode image sub-band components encoded as H.264 video.

17. The image signal processor chip of claim 16, wherein upscaling the image data comprises decoding the one or more of the image sub-band components using the H.264 engine.

18. The image signal processor chip of claim 15, wherein the image signal processor chip further comprises an VC-5 engine configured to decode image sub-band components encoded as VC-5 video.

19. The image signal processor chip of claim 18, wherein upscaling the image data comprises decoding the one or more of the image sub-band components using the VC-5 engine.

20. The image signal processor chip of claim 15, wherein the downscale engine is configured to downscale the image data by outputting a low/low image sub-band component.