Method of programming nonvolatile memory device

• US 9,818,475 B2
• Filed: 01/21/2016
• Issued: 11/14/2017
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jang, Joon-Suc, Kwak, Dong-Hun
• Primary Examiner(s): King, Douglas
• Application Number:
  US15/003,072
• Publication Number:
  US 20160141025A1
• Time in Patent Office: 663 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.

Claims

1. A method of programming a nonvolatile memory device including a plurality of first multi-level cells coupled to a first wordline and a plurality of second multi-level cells coupled to a second wordline adjacent to the first wordline, the method comprising:

performing a first least significant bit (LSB) program operation that programs LSBs of first multi-bit data in the plurality of first multi-level cells;

performing a second LSB program operation that programs LSBs of second multi-bit data in the plurality of second multi-level cells; and

performing, after the second LSB program operation is performed, a first most significant bit (MSB) program operation that programs MSBs of the first multi-bit data in the plurality of first multi-level cells, the first MSB program operation including a first MSB pre-program operation that pre-programs, to an intermediate program state, third multi-level cells from among the plurality of first multi-level cells that are to be programmed to a highest target program state among a plurality of target program states, and a first MSB main program operation that programs the plurality of first multi-level cells to the plurality of target program states corresponding to the first multi-bit data, the first MSB pre-program operation and the first MSB main program operation being performed in one sequence, and

the first MSB pre-program operation including,

applying a program voltage to first bitlines coupled to the third multi-level cells; and

applying an inhibit voltage to second bitlines coupled to fourth multi-level cells other than the third multi-level cells from among the plurality of first multi-level cells, the fourth multi-level cells including ones of the plurality of first multi-level cells that are to be programmed to one of the plurality of target program states adjacent to the highest target program state, and the inhibit voltage being higher than the program voltage, wherein

during the first MSB main program operation, a same programming step programs the third multi-level cells having the intermediate program state and the fourth multi-level cells.

2. The method of claim 1, wherein the third multi-level cells are programmed by the first MSB main program operation from the intermediate program state to the highest target program state having a width narrower than a width of the intermediate program state.

3. The method of claim 1, wherein the program voltage applied to the first bitlines during the first MSB pre-program operation is a ground voltage.

4. The method of claim 1, wherein the program voltage applied to the first bitlines during the first MSB pre-program operation is a voltage higher than a ground voltage.

5. The method of claim 1, further comprising:

performing, after a third LSB program operation for a plurality of fifth multi-level cells coupled to a third wordline adjacent to the second wordline is performed, a second MSB program operation that programs MSBs of the second multi-bit data in the plurality of second multi-level cells, the second MSB program operation including a second MSB pre-program operation and a second MSB main program operation that are performed in one sequence.

6. The method of claim 1, wherein the first MSB pre-program operation further comprises:

applying a one-shot pulse to the first wordline to pre-program the third multi-level cells to an intermediate program state corresponding to the highest target program state.

7. The method of claim 6, wherein the one-shot pulse has a voltage level sufficient to substantially increase a threshold voltage of at least one of the third multi-level cells.

8. The method of claim 1, wherein a verify operation for the intermediate program state is not performed.

9. A nonvolatile memory device comprising:

a memory cell array including a plurality of first multi-level cells coupled to a first wordline and a plurality of second multi-level cells coupled to a second wordline adjacent to the first wordline;

a voltage generator configured to generate a first incremental step pulse, a one-shot pulse, and a second incremental step pulse; and

a control circuit configured

to perform a first least significant bit (LSB) program operation that programs LSBs of first multi-bit data in the plurality of first multi-level cells by using the first incremental step pulse;

to perform a second LSB program operation that programs LSBs of second multi-bit data in the plurality of second multi-level cells by using the first incremental step pulse; and

to perform, after the second LSB program operation is performed, a first most significant bit (MSB) program operation that programs MSBs of the first multi-bit data in the plurality of first multi-level cells, the first MSB program operation including a first MSB pre-program operation that pre-programs third multi-level cells from among the plurality of first multi-level cells to an intermediate program state by using the one-shot pulse, the third multi-level cells being ones of the plurality of first multi-level cells that are to be programmed to a highest target program state among a plurality of target program states, and a first MSB main program operation, separate from the first MSB pre-program operation, that programs the plurality of first multi-level cells to the plurality of target program states corresponding to the first multi-bit data by using the second incremental step pulse, the first MSB main program operation including a verify operation to verify that the plurality of first multi-level cells are programmed to the plurality of target program states, the first MSB pre-program operation and the first MSB main program operation being performed in one sequence, and

the first MSB pre-program operation comprising,

applying a program voltage to first bitlines coupled to the third multi-level cells;

applying an inhibit voltage to second bitlines coupled to fourth multi-level cells other than the third multi-level cells from among the plurality of first multi-level cells, the fourth multi-level cells including ones of the plurality of first multi-level cells that are to be programmed to one of the plurality of target program states adjacent to the highest target program state, and the inhibit voltage being higher than the program voltage; and

applying the one-shot pulse to the first wordline to pre-program the third multi-level cells to the intermediate program state corresponding to the highest target program state,

wherein a verify operation for the intermediate program state is not performed, and

the intermediate program state is lower than the highest target program state and higher than the one of the plurality of target program states adjacent to the highest target program state.

10. The nonvolatile memory device of claim 9, wherein the third multi-level cells are programmed by the first MSB main program operation from the intermediate program state to the highest target program state having a width narrower than a width of the intermediate program state.

11. The nonvolatile memory device of claim 9, wherein the voltage generator generates the one-shot pulse having a voltage level sufficient to substantially increase a threshold voltage of at least one of the first multi-level cells.

12. The nonvolatile memory device of claim 9, wherein the program voltage applied to the first bitlines during the first MSB pre-program operation is a ground voltage.

13. The nonvolatile memory device of claim 9, wherein the program voltage applied to the first bitlines during the first MSB pre-program operation is a voltage higher than a ground voltage.

14. The nonvolatile memory device of claim 9, wherein the control circuit further performs, after a third LSB program operation for a plurality of fifth multi-level cells coupled to a third wordline adjacent to the second wordline is performed, a second MSB program operation that programs MSBs of the second multi-bit data in the plurality of second multi-level cells, and the second MSB program operation includes a second MSB pre-program operation and a second MSB main program operation that are performed in one sequence.