Systems, methods, and apparatus for memory cells with common source lines

• US 9,818,484 B2
• Filed: 03/22/2017
• Issued: 11/14/2017
• Est. Priority Date: 12/02/2013
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Yu, Xiaojun, Prabhakar, Venkatraman, Kouznetsov, Igor G., Hinh, Long T, Jin, Bo
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/466,593
• Publication Number:
  US 20170278573A1
• Time in Patent Office: 237 Days
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Claims

1. An apparatus, comprising:

a first cell including a first control gate and a first select gate;

a second cell including a second control gate and a second select gate;

a third cell including a third control gate and a third select gate;

a fourth cell including a fourth control gate and a fourth select gate,

wherein,

the first, second, third, and fourth cells share a common source line,

the first and second cells share a first select gate line and a first control gate line,

the third and fourth cells share a second select gate line and a second control gate line,

the first and third cells share a first bit line, and the second and the fourth cells share a second bit lines, and

the first and second select gate lines and control gate lines, and the common source line extend perpendicularly to the first and second bit lines.

2. The apparatus of claim 1, wherein the first and second select gate lines and control gate lines, and the common source line are disposed on a same level.

3. The apparatus of claim 1, wherein the first and second bit lines are disposed on a same level, overlying the first and second select gate lines and control gate lines, and the common source line.

4. The apparatus of claim 2, wherein the common source line is electrically coupled to the first and third cells, and the second and fourth cells via first and second contacts, respectively.

5. The apparatus of claim 3, wherein the first bit line is electrically coupled to the first cell via a first via, a bit line contact region, and a bit line contact, and wherein the bit line contact region is disposed at the same level as the first and second select gate lines and control gate lines, and the common source line.