Semiconductor memory device
First Claim
1. A semiconductor memory device, comprising:
- a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string, the first memory string including a first transistor, a second transistor and a plurality of first memory cells, the second memory string including a third transistor, a fourth transistor and a plurality of second memory cells;
a first bit line connected to a node of the first transistor and a node of the third transistor;
a first select gate line connected to a gate of the first transistor;
a second select gate line connected to a gate of the third transistor;
a source line connected to a node of the second transistor and a node of the fourth transistor;
a plurality of word lines, each of the word lines connected to one of gates of the first memory cells and one of gates of the second memory cells;
a controller configured to control an erase verify operation of the memory block, wherein the erase verify operation includes;
applying a first selection voltage to the first select gate line at a first time;
while applying the first selection voltage to the first select gate line, applying an erase verify voltage to the plurality of word lines; and
applying a second selection voltage to the second select gate line at a second time after the first time without making the voltage applied to the plurality of word lines zero voltage at any time between the first time and the second time.
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Accused Products
Abstract
A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.
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Citations
20 Claims
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1. A semiconductor memory device, comprising:
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a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string, the first memory string including a first transistor, a second transistor and a plurality of first memory cells, the second memory string including a third transistor, a fourth transistor and a plurality of second memory cells; a first bit line connected to a node of the first transistor and a node of the third transistor; a first select gate line connected to a gate of the first transistor; a second select gate line connected to a gate of the third transistor; a source line connected to a node of the second transistor and a node of the fourth transistor; a plurality of word lines, each of the word lines connected to one of gates of the first memory cells and one of gates of the second memory cells; a controller configured to control an erase verify operation of the memory block, wherein the erase verify operation includes; applying a first selection voltage to the first select gate line at a first time; while applying the first selection voltage to the first select gate line, applying an erase verify voltage to the plurality of word lines; and applying a second selection voltage to the second select gate line at a second time after the first time without making the voltage applied to the plurality of word lines zero voltage at any time between the first time and the second time. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor memory device, comprising:
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a plurality of memory strings, each of the memory strings including a first transistor, a second transistor and a plurality of memory cells serially connected between the first transistor and the second transistor, the plurality of memory strings including a first memory string and a second memory string; a first bit line connected to nodes of the first transistors in the first memory string and the second memory string; a first select gate line connected to a gate of the first transistor of the first memory string; a second select gate line connected to a gate of the first transistor of the second memory string; a plurality of word lines connected to at least gates of memory cells of the first memory string and the second memory string; a controller configured to control an erase verify operation of the plurality of memory strings, wherein the erase verify operation includes; applying a first selection voltage to the first select gate line at a first time; while applying the first selection voltage to the first select gate line, applying an erase verify voltage to the plurality of word lines; and applying a second selection voltage to the second select gate line at a second time after the first time without making the voltage applied to the plurality of word lines zero voltage at any time between the first time and the second time. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A semiconductor memory device, comprising:
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a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string, the first memory string including a first transistor, a second transistor and a plurality of first memory cells, the second memory string including a third transistor, a fourth transistor and a plurality of second memory cells; a first bit line connected to a node of the first transistor and a node of the third transistor; a first select gate line connected to a gate of the first transistor; a second select gate line connected to a gate of the third transistor; a source line connected to a node of the second transistor and a node of the fourth transistor; a plurality of word lines, each of the word lines connected to one of gates of the first memory cells and one of gates of the second memory cells; a controller configured to control an erase verify operation of the memory block, wherein the erase verify operation includes; applying a first selection voltage to the first select gate line at a first time; while applying the first selection voltage to the first select gate line, applying an erase verify voltage to the plurality of word lines; and applying a second selection voltage to the second select gate line at a second time after the first time while keeping constant the voltage applied to the plurality of word lines between the first time and the second time. - View Dependent Claims (13, 14, 15, 16)
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17. A semiconductor memory device, comprising:
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a memory block including a plurality of memory strings, each of the memory strings being coupled to a different select gate line, the memory strings being coupled to a common bit line, the memory block being a unit of an erase verify operation; and a controller configured to control the erase verify operation of the memory block, wherein the erase verify operation includes; selecting one of the memory strings at a first time; while selecting the one of the memory strings, applying an erase verify voltage to the memory strings; and selecting another one of the memory strings at a second time after the first time while keeping constant the voltage applied to the memory strings between the first time and the second time. - View Dependent Claims (18, 19, 20)
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Specification