Operation recording circuit and operation method thereof

• US 9,818,494 B2
• Filed: 07/29/2014
• Issued: 11/14/2017
• Est. Priority Date: 01/29/2014
• Status: Active Grant

• Current Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Original Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Inventors: Lu, Chia-Ching
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): TAYLOR, BROOKE JAZMOND
• Application Number:
  US14/445,078
• Publication Number:
  US 20150212916A1
• Time in Patent Office: 1,204 Days
• Field of Search: 710 18
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/46 Test trigger logic

Abstract

An operation recording circuit and an operation method thereof are provided. The operation recording circuit includes a pin monitor unit, a memory unit, a data writing unit, a mode verification unit and a data dumping unit. The pin monitor unit monitors at least one first type pin of an integrated circuit (IC) to correspondingly provide a monitor signal. The data writing unit writes at least one monitor records into the memory unit according the monitor signal. When receiving a test dump command through at least one second type pin of the IC, the mode verification unit correspondingly provides a dump control signal. The data dumping unit determines whether to output the at least one monitor records from the memory unit through the at least one second type pin or not according to the dump control signal.

Claims

1. An operation recording circuit, embedded in an integrated circuit (IC) to be monitored, the operation recording circuit comprising:

a pin monitor unit, coupled to at least one first type pin of the integrated circuit (IC) to monitor the at least one first type pin and correspondingly provide a monitor signal which indicates a level of an electric signal transmitted on the at least one first type pin during an operation of the integrated circuit, wherein the at least one first type pin is set by a main function circuit, and the main function circuit is embedded in the IC and different from the operation recording circuit;

a memory unit, wherein the operation of the memory unit is independent from the main function circuit;

a data writing unit, coupled to the pin monitor unit and the memory unit and configured to receive the monitor signal and write at least one monitor record into the memory unit according to the monitor signal;

a mode verification unit, coupled to at least one second type pin of the IC and configured to correspondingly provide a dump control signal after receiving a test dump command through the at least one second type pin;

a data dumping unit, coupled to the at least one second type pin, the memory unit and the mode verification unit to receive the dump control signal and configured to determine whether to output the at least one monitor records from the memory unit through the at least one second type pin according to the dump control signal;

wherein I/O state of the at least one first type pin and the at least one second type pin is set by an IO control unit which is controlled by the main function circuit, the IO control unit and the main function circuit are located in the IC, and the mode verification unit is further coupled to the IO control unit and outputs a pin lock signal to disable the IO control unit when the at least one second type pin receives the test dump command.

2. The operation recording circuit according to claim 1, further comprising:

a timing unit, coupled to the data writing unit to provide a monitor timing signal, wherein the data writing unit writes the at least one monitor records corresponding to the monitor signal into the memory unit according to the monitor timing signal.

3. The operation recording circuit according to claim 1, further comprising:

a trigger unit, coupled to the data writing unit to provide a monitor trigger signal, wherein the data writing unit performs write protection or starts the data writing on the memory unit according to the monitor trigger signal.

4. The operation recording circuit according to claim 3, wherein the trigger unit sets the monitor trigger signal according to an operation state of the IC, and when the operation state of the IC satisfies a monitor condition, the trigger unit enables the monitor trigger signal.

5. The operation recording circuit according to claim 4, wherein the trigger unit is coupled to at least one third type pin of the IC to determine the operation state of the IC according to a voltage level of the at least one third type pin.

6. The operation recording circuit according to claim 1, wherein when the data writing unit writes the at least one monitor records into the memory unit, the data writing unit sets a monitor flag, when the monitor flag is set as a set state, the mode verification unit determines whether the at least one second type pins receives the test dump command according to the monitor flag, and when outputting the at least one monitor records from the memory unit through the at least one second type pin, the data dumping unit notifies the mode verification unit to set the monitor flag as a reset state.

7. The operation recording circuit according to claim 6, wherein the monitor flag is configured in the data writing unit or the memory unit.

8. The operation recording circuit according to claim 6, wherein when the IC starts to operate, and the monitor flag is set as a reset state, the data writing unit performs initialization on the memory unit.

9. An operation method of an operation recording circuit embedded in an integrated circuit (IC) to be monitored, comprising:

monitoring at least one first type pin of the IC and correspondingly providing a monitor signal by a pin monitor unit, wherein the monitor signal indicates a level of an electric signal transmitted on the at least one first type pin during an operation of the integrated circuit, wherein the at least one first type pin is set by a main function circuit, and the main function circuit is embedded in the and different from the operation recording circuit;

writing at least one monitor record corresponding to the monitor signal into a memory unit by a data writing unit, wherein the operation of the memory unit is independent from the main function circuit;

when a test dump command is received by at least one second type pin of the IC, correspondingly providing a dump control signal by a mode verification unit;

and determining whether to output the at least one monitor record from the memory unit through the at least one second type pin or not according to the dump control signal by a data dumping unit;

coupling an IO control unit to the at least one first type pin and the at least one second type pin;

setting an IO state of the at least one first type pin and an IO state of the at least one second type pin by the IO control which is controlled by the main function circuit;

and when the test dump command is received by the at least one second type pin, disabling the IO control unit;

the mode verification unit is further coupled to the IO control unit and outposts a pin lock signal to disable the IO control unit when the at least one second type pin receives the test dump command.

10. The operation method according to claim 9, wherein the pin monitor unit monitors an operation log of the at least one first type pin.

11. The operation method according to claim 9, wherein the step of writing the at least one monitor records corresponding to the monitor signal into the memory unit by the data writing unit comprises:

writing the at least one monitor records corresponding to the monitor signal into the memory unit by the data writing unit according to a monitor timing signal provided by a timing unit.

12. The operation method according to claim 9, wherein the step of writing the at least one monitor records corresponding to the monitor signal into the memory unit by the data writing unit comprises:

performing write protection on the memory unit by the data writing unit according to a monitor trigger signal provided by a trigger unit.

13. The operation method according to claim 12, further comprising:

when an operation state of the IC satisfies a monitor condition, enabling the monitor trigger signal by the trigger unit.

14. The operation method according to claim 13, further comprising:

determining the operation state of the IC by the trigger unit according to a voltage level of at least one third type pin of the IC.

15. The operation method according to claim 9, further comprising:

when the at least one monitor records is written into the memory unit, setting a monitor flag;

when the monitor flag is set as a set state, determining whether the test dump command is received by the at least one second type pin;

and when the at least one monitor records is outputted through the at least one second type pin, setting the monitor flag as a reset state.

16. The operation method according to claim 15, further comprising:

when the IC starts to operate, and the monitor flag is set as a reset state, initializing the memory unit.

17. The operation method according to claim 10, wherein the operation log comprises records with respect to monitoring a voltage level, a current level, a change of the voltage level or a change of the current level on the at least one first type pin for generating the monitor signal.