Method for forming Fin field effect transistor (FinFET) device structure
First Claim
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1. A method for forming a fin field effect transistor (FinFET) device structure, comprising:
- forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively, wherein a number of the first fin structures is greater than a number of the second fin structures;
forming a sacrificial layer on the first fin structures and the second fin structures; and
performing an etching process to the sacrificial layer to form an isolation structure on the substrate;
forming a dummy gate structure on a middle portion of the first fin structures and the second fin structures;
removing a portion of a top portion of the first fin structures to form a cavity;
forming a source/drain structure in the cavity and on the cavity; and
forming the inter-layer dielectric (ILD) structure on the S/D structure and the dummy gate structure.
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Abstract
Methods for forming the fin field effect transistor (FinFET) device structure are provided. The method includes forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively, and a number of the first fin structures is greater than a number of the second fin structures. The method also includes forming a sacrificial layer on the first fin structures and the second fin structures and performing an etching process to the sacrificial layer to form an isolation structure on the substrate.
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Citations
18 Claims
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1. A method for forming a fin field effect transistor (FinFET) device structure, comprising:
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forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively, wherein a number of the first fin structures is greater than a number of the second fin structures; forming a sacrificial layer on the first fin structures and the second fin structures; and performing an etching process to the sacrificial layer to form an isolation structure on the substrate; forming a dummy gate structure on a middle portion of the first fin structures and the second fin structures; removing a portion of a top portion of the first fin structures to form a cavity; forming a source/drain structure in the cavity and on the cavity; and forming the inter-layer dielectric (ILD) structure on the S/D structure and the dummy gate structure. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for forming a fin field effect transistor (FinFET) device structure, comprising:
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forming first fin structures and the second fin structures on a first region and a second region of a substrate, respectively, wherein forming the first fin structures and the second fin structures on the first region and the second region comprises; forming third fin structures on the second region, wherein the number of the first fin structures on the first region is equal to a sum of a number of the third fin structures and the number of the second fin structure on the second region; and removing the third fin structures, such that the number of the first fin structures on the first region is greater than the number of the second fin structures on the second region; forming a hard mask layer over the first fin structures and the second fin structures; forming a dielectric layer on the hard mask layer; and performing an etching process to the dielectric layer to form an isolation structure on the substrate, wherein the isolation structure is lower than a top surface of the first fin structures and the second fin structures. - View Dependent Claims (9, 10, 11, 12)
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13. A method for forming a fin field effect transistor (FinFET) device structure, comprising:
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forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively; forming a hard mask layer over the first fin structures and the second fin structures; forming a dielectric layer on the hard mask layer; thinning the dielectric layer to expose a top surface of the hard mask layer, such that a top surface of the dielectric layer is level with a top surface of the hard mask layer; removing the hard mask layer to expose top surfaces of the first fin structures and top surfaces of the second fin structures; forming a sacrificial layer on the dielectric layer, the first fin structures and the second fin structures; and performing an etching process to the sacrificial layer to form an isolation structure on the substrate. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification