Method and structure for FinFET isolation

• US 9,818,649 B2
• Filed: 11/07/2016
• Issued: 11/14/2017
• Est. Priority Date: 10/17/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Lin, Jr-Jung
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US15/345,125
• Publication Number:
  US 20170076989A1
• Time in Patent Office: 372 Days
• Field of Search: 257401
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a substrate having first and second fins extending lengthwise generally along a same line; a first gate stack over the substrate and engaging the first fin; a second gate stack over the substrate and engaging the second fin; a first isolation structure disposed between the first and second fins; and spacer features on sidewalls of the first and second gate stacks and on sidewalls of an upper portion of the first isolation structure.

Claims

1. A semiconductor device, comprising:

a substrate having first and second fins extending lengthwise generally along a same line;

a first gate stack over the substrate and engaging the first fin;

a second gate stack over the substrate and engaging the second fin;

a first isolation structure disposed between the first and second fins; and

spacer features on sidewalls of the first and second gate stacks and on sidewalls of an upper portion of the first isolation structure.

2. The semiconductor device of claim 1, further comprising:

a second isolation structure over the substrate, wherein the first and second fins protrude above a top surface of the second isolation structure, and wherein the first and second gate stacks are disposed over the top surface of the second isolation structure.

3. The semiconductor device of claim 2, wherein a portion of the first isolation structure is below the top surface of the second isolation structure.

4. The semiconductor device of claim 2, wherein a portion of the first isolation structure is disposed over another surface of the second isolation structure that is below the top surface of the second isolation structure.

5. The semiconductor device of claim 1, further comprising:

a dielectric material between the first isolation structure and each of the first and second fins.

6. The semiconductor device of claim 5, wherein the dielectric material layer comprises silicon oxide or silicon nitride.

7. The semiconductor device of claim 5, wherein the dielectric material layer has a thickness of 5 to 100 angstroms (Å

).

8. The semiconductor device of claim 1, wherein a portion of the first fin is underneath the spacer features that are on the sidewalls of the upper portion of the first isolation structure.

9. A semiconductor device, comprising:

a substrate having first and second fins extending lengthwise generally along a same direction;

a first isolation structure over the substrate, wherein the first and second fins protrude above a top surface of the first isolation structure;

first and second gate stacks over the top surface of the first isolation structure and engaging the first and second fins respectively;

a second isolation structure disposed between the first and second fins and between the first and second gate stacks; and

spacer features on sidewalls of the first and second gate stacks and on sidewalls of an upper portion of the second isolation structure.

10. The semiconductor device of claim 9, wherein a portion of the second isolation structure is disposed below the top surface of the first isolation structure.

11. The semiconductor device of claim 9, wherein a portion of the second isolation structure is disposed over another surface of the first isolation structure that is below the top surface of the first isolation structure.

12. The semiconductor device of claim 9, wherein the second isolation structure directly contacts the first and second fins.

13. The semiconductor device of claim 9, further comprising:

a dielectric material between the second isolation structure and each of the first and second fins.

14. The semiconductor device of claim 9, wherein a portion of the first fin and another portion of the second fin are underneath the spacer features that are on the sidewalls of the upper portion of the second isolation structure.

15. A semiconductor device, comprising:

a substrate having first and second fins extending lengthwise generally along a same direction, wherein a first end of the first fin is adjacent to a first end of the second fin;

a first gate stack over the substrate and engaging the first fin;

a second gate stack over the substrate and engaging the second fin;

a first isolation structure over a second end of the first fin from a top view;

a second isolation structure over a second end of the second fin from the top view; and

a third isolation structure adjacent to both the first end of the first fin and the first end of the second fin from the top view.

16. The semiconductor device of claim 15, further comprising:

spacer features on sidewalls of each of the first, second, and third isolation structures.

17. The semiconductor device of claim 15, further comprising:

a fourth isolation structure over the substrate, wherein the first and second gate stacks are disposed over the fourth isolation structure.

18. The semiconductor device of claim 17, wherein:

the first and second gate stacks are disposed over a first surface of the fourth isolation structure; and

the third isolation structure is disposed over a second surface of the fourth isolation structure, wherein the second surface is lower than the first surface from a cross sectional view.

19. The semiconductor device of claim 15, further comprising:

a dielectric material between the third isolation structure and each of the first end of the first fin and the first end of the second fin.

20. The semiconductor device of claim 19, wherein the dielectric material layer comprises silicon oxide or silicon nitride.