Storage element, storage device, and signal processing circuit

• US 9,818,749 B2
• Filed: 04/12/2016
• Issued: 11/14/2017
• Est. Priority Date: 01/05/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohmaru, Takuro, Endo, Masami
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/096,368
• Publication Number:
  US 20160225774A1
• Time in Patent Office: 581 Days
• Field of Search: 257 43, 327208
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/26 including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Claims

1. A semiconductor device comprising:

a first transistor over a substrate, the first transistor comprising a channel formation region comprising a silicon;

an insulating film over the first transistor;

a second transistor over the insulating film, the second transistor comprising a channel formation region comprising an oxide semiconductor material;

a third transistor;

a capacitor; and

a storage circuit,

wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor,

wherein one of a pair of electrodes of the capacitor is electrically connected to the one of the source and the drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the storage circuit, and

wherein one of a source and a drain of the third transistor is electrically connected to the storage circuit.

4. The semiconductor device according to claim 1, wherein the storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

7. The semiconductor device according to claim 1, wherein the second transistor overlaps with the first transistor with the insulating film interposed therebetween.

10. The semiconductor device according to claim 1, wherein the other of the source and the drain of the second transistor is electrically connected to an output terminal of the storage circuit.

13. The semiconductor device according to claim 1, wherein the one of the source and the drain of the third transistor is electrically connected to an input terminal of the storage circuit.

16. The semiconductor device according to claim 1, wherein the storage circuit is a volatile storage circuit.

2. A semiconductor device comprising:

a first transistor over a substrate, the first transistor comprising a channel formation region comprising a silicon;

an insulating film over the first transistor;

a second transistor over the insulating film, the second transistor comprising a channel formation region comprising an oxide semiconductor material;

a third transistor;

a fourth transistor;

a capacitor; and

a storage circuit,

wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein one of a pair of electrodes of the capacitor is electrically connected to the one of the source and the drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the storage circuit, and

wherein the other of the source and the drain of the fourth transistor is electrically connected to the storage circuit.

5. The semiconductor device according to claim 2, wherein the storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

8. The semiconductor device according to claim 2, wherein the second transistor overlaps with the first transistor with the insulating film interposed therebetween.

11. The semiconductor device according to claim 2, wherein the other of the source and the drain of the second transistor is electrically connected to an output terminal of the storage circuit.

14. The semiconductor device according to claim 2, wherein the other of the source and the drain of the fourth transistor is electrically connected to an input terminal of the storage circuit.

17. The semiconductor device according to claim 2, further comprising a fifth transistor, one of a source and a drain of the fifth transistor being electrically connected to the other of the source and the drain of the fourth transistor.

18. The semiconductor device according to claim 17, wherein a gate of the fourth transistor is electrically connected to a gate of the fifth transistor.

3. A semiconductor device comprising:

a first transistor over a substrate, the first transistor comprising a channel formation region comprising a silicon;

a first insulating film over the first transistor;

a first wiring over the first insulating film;

a second insulating film over the first wiring;

a second wiring over the second insulating film;

a third insulating film over the second wiring;

a second transistor over the third insulating film, the second transistor comprising a channel formation region comprising an oxide semiconductor material;

a third transistor; and

a storage circuit,

wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the storage circuit, and

wherein one of a source and a drain of the third transistor is electrically connected to the storage circuit.

6. The semiconductor device according to claim 3, wherein the storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

9. The semiconductor device according to claim 3, wherein the second transistor overlaps with the first transistor with the first insulating film, the first wiring, the second insulating film, the second wiring, and the third insulating film interposed therebetween.

12. The semiconductor device according to claim 3, wherein the other of the source and the drain of the second transistor is electrically connected to an output terminal of the storage circuit.

15. The semiconductor device according to claim 3, wherein the one of the source and the drain of the third transistor is electrically connected to an input terminal of the storage circuit.

19. The semiconductor device according to claim 3, wherein the first wiring is electrically connected to the one of the source and the drain of the second transistor.

20. A signal processing circuit comprising:

a register, the register comprising;

a first storage circuit including a first inverter and a second inverter; and

a second storage circuit, the second storage circuit comprising;

a capacitor comprising a pair of electrodes;

a first transistor; and

a second transistor,

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,

wherein the second transistor comprises a channel formation region comprising a silicon,

wherein a data stored in the first storage circuit is configured to be input to one of the pair of electrodes and a gate of the second transistor through the first transistor, and

wherein one of a source and a drain of the second transistor is electrically connected to the first storage circuit.

22. The signal processing circuit according to claim 20, wherein the first storage circuit is configured to hold the data only in a period during which a power supply voltage supplied.

24. The signal processing circuit according to claim 20, wherein the one of the source and the drain of the second transistor is electrically connected to an input terminal of the first storage circuit.

21. A signal processing circuit comprising:

a register, the register comprising;

a first storage circuit;

a second storage circuit, the second storage circuit comprising;

a capacitor comprising a pair of electrodes;

a first transistor; and

a second transistor,

a first switch comprising a first terminal and a second terminal; and

a second switch comprising a first terminal and a second terminal;

wherein the first storage circuit is a volatile storage circuit;

wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material;

wherein the second transistor comprises a channel formation region comprising a silicon,

wherein one of a source and a drain of the first transistor is electrically connected to one of the pair of electrodes and a gate of the second transistor;

wherein one of a source and a drain of the second transistor is electrically connected to a first power supply line;

wherein the other of the source and the drain of the second transistor is electrically connected to the first terminal of the first switch;

wherein the second terminal of the first switch is electrically connected to the first terminal of the second switch;

wherein the second terminal of the second switch is electrically connected to a second power supply line;

wherein the other of the source and the drain of the first transistor is electrically connected to the first storage circuit; and

wherein the second terminal of the first switch is electrically connected to the first storage circuit.

23. The signal processing circuit according to claim 21, wherein the first storage circuit is configured to hold a data only in a period during which a power supply voltage supplied.

25. The signal processing circuit according to claim 21, wherein the second terminal of the first switch is electrically connected to an input terminal of the first storage circuit.