Self aligned semiconductor device and structure

• US 9,818,800 B2
• Filed: 11/26/2014
• Issued: 11/14/2017
• Est. Priority Date: 10/11/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak C., Or-Bach, Zvi
• Primary Examiner(s): NGUYEN, DUY T V
• Application Number:
  US14/555,494
• Publication Number:
  US 20150123072A1
• Time in Patent Office: 1,084 Days
• Field of Search: 257 5, 257202
• CPC Class Codes: H01L 2029/7857 of the accumulation type
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 : of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 : arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A device, including: a first layer including first transistors and a second layer including second transistors, where at least one of the first transistors is self-aligned to one of the second transistors, where the second transistors are horizontally oriented transistors, and where the second layer includes a plurality of resistive-random-access memory (RRAM) cells, the memory cells including the second transistors.

Claims

1. A 3D semiconductor device, the device comprising:

a plurality of first transistors, overlaid by a plurality of second transistors, overlaid by a plurality of third transistors, overlaid by a plurality of fourth transistors,

wherein said second transistors, said third transistors and said fourth transistors are self-aligned, having been processed following the same lithography step, and

wherein at least one of said first transistors is part of a control circuit controlling at least one of said second transistors, at least one of said third transistors and at least one of said fourth transistors.

2. The device according to claim 1,

wherein said third transistors are junction-less transistors, and

wherein said junction-less transistors comprise a single crystal channel.

3. The device according to claim 1,

wherein said third transistors are junction-less transistors, and

wherein said junction-less transistors comprise a polysilicon channel.

4. The device according to claim 1,

wherein said third transistors are junction-less transistors.

5. The device according to claim 1,

wherein said first transistors comprise a single crystal channel.

6. The device according to claim 1, further comprising:

a memory cell,

wherein said memory cell comprises at least one of said third transistors.

7. The device according to claim 1, further comprising:

a memory peripheral circuit,

wherein said memory peripheral circuit comprises at least one of said first transistors.

8. A 3D semiconductor device, the device comprising:

a plurality of first transistors, overlaid by a plurality of second memory cells, overlaid by a plurality of third memory cells, overlaid by a plurality of fourth memory cells,

wherein said second memory cells, said third memory cells and said fourth memory cells are self-aligned, having been processed following the same lithography step, and

wherein at least one of said first transistors is part of a control circuit controlling at least one of said second memory cells, at least one of said third memory cells and at least one of said fourth memory cells, and

wherein at least one of said second memory cells comprises second transistors, at least one of said second transistors is a junction-less transistor.

9. The device according to claim 8,

wherein said third memory cells comprise at least one junction-less transistor, and

wherein said at least one junction-less transistor comprises a single crystal channel.

10. The device according to claim 8,

wherein said third memory cells comprise at least one junction-less transistor, and

wherein said at least one junction-less transistor comprises a polysilicon channel.

11. The device according to claim 8,

wherein said third memory cells comprise at least one junction-less transistor.

12. The device according to claim 8,

wherein said first transistors comprise a single crystal channel.

13. The device according to claim 8, further comprising:

a memory cells peripheral circuit,

wherein said memory cells peripheral circuit comprises at least one of said first transistors.

14. The device according to claim 8,

wherein at least one of said second memory cells is overlaying said at least one of said first transistors.

15. A 3D semiconductor device, the device comprising:

a plurality of first transistors, overlaid by a plurality of second transistors, overlaid by a plurality of third transistors, overlaid by a plurality of fourth transistors,

wherein said second transistors, said third transistors and said fourth transistors are self-aligned, having been processed following the same lithography step, and

wherein at least one of said first transistors is part of a memory peripheral circuit controlling at least one of said second transistors, at least one of said third transistors and at least one of said fourth transistors, and

a first memory cell,

wherein said first memory cell comprises at least one of said second transistors.

16. The device according to claim 15,

wherein said third transistors are junction-less transistors, and

wherein said junction-less transistors comprise a single crystal channel.

17. The device according to claim 15,

wherein said third transistors are junction-less transistors, and

wherein said junction-less transistors comprise a polysilicon channel.

18. The device according to claim 15,

wherein said third transistors are junction-less transistors.

19. The device according to claim 15,

wherein said first transistors comprise a single crystal channel.

20. The device according to claim 15, further comprising:

a second memory cell,

wherein said second memory cell comprises at least one of said third transistors.