Power semiconductor device including trench gate structures with longitudinal axes tilted to a main crystal direction

• US 9,818,818 B2
• Filed: 03/01/2016
• Issued: 11/14/2017
• Est. Priority Date: 03/03/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Rupp, Roland, Esteve, Romain, Peters, Dethard
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): RHODES, JUANITA B
• Application Number:
  US15/057,669
• Publication Number:
  US 20160260798A1
• Time in Patent Office: 623 Days
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 : Diodes

Abstract

A semiconductor device includes a semiconductor body with a first main crystal direction parallel to a horizontal plane. Longitudinal axes of trench gate structures are tilted to the first main crystal direction by a tilt angle of at least 2 degree and at most 30 degree in the horizontal plane. Mesa portions are between neighboring trench gate structures. First sidewall sections of first mesa sidewalls are main crystal planes parallel to the first main crystal direction. Second sidewall sections tilted to the first sidewall sections connect the first sidewall sections.

Claims

1. A semiconductor device comprising:

a semiconductor body with a first main crystal direction parallel to a horizontal plane,

trench gate structures with a longitudinal extension greater than a width in a same direction of the horizontal plane, wherein a longitudinal axis of each trench gate structure of the trench gate structures is tilted to the first main crystal direction by a tilt angle of at least 2 degree and at most 30 degree in the horizontal plane; and

mesa portions between neighboring trench gate structures, wherein first sidewall sections of first mesa sidewalls are first main crystal planes parallel to the first main crystal direction and second sidewall sections of the first mesa sidewalls tilted to the first sidewall sections connect the first sidewall sections.

2. The semiconductor device of claim 1, wherein

the horizontal plane is parallel to a mean surface plane of the semiconductor body.

3. The semiconductor device of claim 1, wherein

a second main crystal direction orthogonal to the first main crystal direction is tilted to the horizontal plane by an off-axis angle of at least 2 degree.

4. The semiconductor device of claim 1, wherein

a first surface of the semiconductor body comprises first surface sections and second surface sections, which are tilted to the first surface sections and which connect the first surface sections.

5. The semiconductor device of claim 4, wherein

the first surface sections are second main crystal planes parallel to a second main crystal direction.

6. The semiconductor device of claim 3, wherein

the off-axis angle is in a range from 3 to 12 degree.

7. The semiconductor device of claim 1, wherein

the tilt angle is in a range from 3 to 12 degree.

8. The semiconductor device of claim 1, wherein

the semiconductor body has a hexagonal crystal lattice and the first main crystal direction is one of the <

11-20>

crystal direction and the <

1-100>

crystal direction.

9. The semiconductor device of claim 1, wherein

a first surface of the semiconductor body comprises first surface sections formed by (1-100) crystal planes and second surface sections tilted to the first surface sections by an angle greater than 0 degree and connecting the first surface sections.

10. The semiconductor device of claim 1, wherein

a first surface of the semiconductor body comprises first surface sections formed by (11-20) crystal planes and second surface sections tilted to the first surface sections by an angle greater than 0 degree and connecting the first surface sections.

11. The semiconductor device of claim 1, wherein

the semiconductor body is based on silicon carbide of a 4H polytype.

12. The semiconductor device of claim 2, wherein

the mesa portions comprise body zones forming first pn junctions with a drift structure and second pn junctions with source zones, the source zones formed between the body zones and the mean surface plane.

13. The semiconductor device of claim 12, further comprising:

diode regions forming third pn junctions with the drift structure and overlapping with the trench gate structures in a vertical projection orthogonal to the mean surface plane.

14. The semiconductor device of claim 1, wherein

the trench gate structures taper at a taper angle which deviates from an off-axis angle by not more than ±

1 degree.

15. The semiconductor device of claim 1, wherein

a depth of the trench gate structures is in a range from 0.5 μ

m to 2.0 μ

m.