Integrated RF front end system

• US 9,818,821 B2
• Filed: 07/21/2016
• Issued: 11/14/2017
• Est. Priority Date: 06/28/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: McPartlin, Michael Joseph, Doherty, Mark M.
• Primary Examiner(s): Nguyen, Tuan H
• Application Number:
  US15/216,620
• Publication Number:
  US 20170018607A1
• Time in Patent Office: 481 Days
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 2223/665 Bias feed arrangements
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/067 Lateral bipolar transistor in combination with diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0823 including vertical bipolar transistors only
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0821 : Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0826 : Pedestal collectors
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66242 : Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/737 : Hetero-junction transistors
• CPC Class Codes: H01L 29/7371 : Vertical transistors
• CPC Class Codes: H01L 29/7378 : comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01Q 1/24 : with receiving set
• CPC Class Codes: H03F 2200/222 : A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/318 : A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/387 : A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 : the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/245 : with semiconductor devices only

Abstract

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

Claims

1. A semiconductor device for an integrated front-end module comprising:

a high-resistivity bulk silicon substrate having a first impurity type and a top surface that lies in a top plane;

a silicon germanium bipolar transistor disposed above the high-resistivity bulk silicon substrate;

a well located between the silicon germanium bipolar transistor and a passive device, the well providing at least partial electrical isolation between the silicon germanium bipolar transistor and the passive device; and

a trench disposed between a sub-collector region of the silicon germanium bipolar transistor and the well, the trench a distance away from the sub-collector region and configured to impede movement across the trench of carriers in the high-resistivity bulk silicon substrate.

2. The semiconductor device of claim 1 wherein the sub-collector region is of a second impurity type that differs from the first impurity type.

3. The semiconductor device of claim 1 further comprising a low-resistivity epitaxial layer disposed adjacent to the top surface and lying in a plane parallel to the top plane.

4. The semiconductor device of claim 3 wherein a resistivity of the low-resistivity epitaxial layer is within a range of around 1-100 Ohms*cm.

5. The semiconductor device of claim 3 wherein the low-resistivity epitaxial layer is of a second impurity type that differs from the first impurity type.

6. The semiconductor device of claim 1 wherein a resistivity of the high-resistivity bulk silicon substrate is at least approximately 1000 Ohms*cm.

7. The semiconductor device of claim 1 wherein the well has a lower resistivity than a resistivity of the high-resistivity bulk silicon substrate.

8. The semiconductor device of claim 1 wherein the trench is adjacent to the well.

9. The semiconductor device of claim 1 wherein the well substantially surrounds the transistor sub-collector region.

10. The semiconductor device of claim 1 wherein a region positioned between the well and the sub-collector region has a resistivity higher than both the well and the sub-collector region.

11. A wireless device comprising:

a front-end module including a high-resistivity bulk silicon substrate, a silicon germanium bipolar transistor, a well, and a trench, the high-resistivity bulk silicon substrate having a first impurity type and a top surface that lies in a top plane, the silicon germanium bipolar transistor disposed above the high-resistivity bulk silicon substrate, the well located between the silicon germanium bipolar transistor and a passive device, the well providing at least partial electrical isolation between the silicon germanium bipolar transistor and the passive device, and the trench disposed between a sub-collector region of the silicon germanium bipolar transistor and the well, the trench a distance away from the sub-collector region and configured to impede movement across the trench of carriers in the high-resistivity bulk silicon substrate; and

an antenna in electrical communication with the front-end module, the antenna configured to receive and transmit wireless signals.

12. The wireless device of claim 11 wherein the high-resistivity bulk silicon substrate has a resistivity of at least approximately 1000 Ohms*cm.

13. The wireless device of claim 11 wherein the high-resistivity bulk silicon substrate has a resistivity of at least approximately 500 Ohms*cm.

14. The wireless device of claim 11 wherein the sub-collector region is of a second impurity type that differs from the first impurity type.

15. The wireless device of claim 11 wherein the front-end module further includes a low-resistivity epitaxial layer disposed adjacent to the top surface and lying in a plane parallel to the top plane.

16. The wireless device of claim 15 wherein a resistivity of the low-resistivity epitaxial layer is within a range of around 1-100 Ohms*cm.

17. The wireless device of claim 15 wherein the low-resistivity epitaxial layer is of a second impurity type that differs from the first impurity type.

18. The wireless device of claim 11 wherein the well has a lower resistivity than a resistivity of the high-resistivity bulk silicon substrate.

19. The wireless device of claim 11 wherein the first impurity type is p-type.

20. The wireless device of claim 11 wherein the well substantially surrounds the transistor sub-collector region.

21. The wireless device of claim 11 wherein a region positioned between the well and the sub-collector region has resistivity characteristics higher than both the well and the sub-collector region.

22. A method of fabricating a front-end module, the method comprising:

creating a high-resistivity bulk silicon substrate in a silicon wafer;

implanting a low-resistivity implant in particular regions of the silicon wafer;

forming a number of active devices on the high-resistivity bulk silicon substrate;

forming one or more passive devices on the high-resistivity bulk silicon substrate; and

forming an epitaxial layer of low-resistivity silicon on the upper surface of the silicon wafer.

23. The method of claim 22 further comprising destroying at least a portion of the epitaxial layer in particular regions of the silicon wafer to restore high-resistivity characteristics of the high-resistivity bulk silicon substrate in the particular regions.