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Fault tolerant design for large area nitride semiconductor devices

  • US 9,818,857 B2
  • Filed: 10/28/2014
  • Issued: 11/14/2017
  • Est. Priority Date: 08/04/2009
  • Status: Active Grant
First Claim
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1. A device structure for a nitride semiconductor transistor comprising:

  • a substrate having a nitride semiconductor layer formed on a device area of the substrate, the nitride semiconductor layer defining a plurality of active regions for an array of islands of a multi-island transistor, the array of islands extending in first and second directions over the device area,each of said active regions comprising a two dimensional electron gas (2DEG) region isolated from adjacent active regions by an intervening inactive region of the device area;

    each island having a source electrode, a drain electrode and a gate electrode formed on a respective active region of the island, each source electrode having a plurality of source peninsulas, each drain electrode having a plurality of drain peninsulas, the source and drain peninsulas being interleaved and spaced apart over the active region of the island to define a channel region therebetween, the gate electrode being formed on the nitride semiconductor layer over the channel region and running between the source and drain peninsulas across the island;

    each source electrode having a source contact area, each drain electrode having a drain contact area and each gate electrode having a gate contact area; and

    the source, drain and gate electrodes of each island of the array of islands having an arrangement wherein each island is electrically isolated from the source, drain and gate electrodes of neighbouring islands in at least one of said first and second directions, andwherein the source, drain and gate contact areas of each island provide for electrical probing and testing of individual islands for identification of defective islands and for selective isolation of a defective island from other islands of the array.

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