Fault tolerant design for large area nitride semiconductor devices

• US 9,818,857 B2
• Filed: 10/28/2014
• Issued: 11/14/2017
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Original Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Inventors: Klowak, Greg P., McKnight-Macneil, Cameron, Tweddle, Howard, Mizan, Ahmad, Springett, Nigel
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US15/032,824
• Publication Number:
  US 20160284829A1
• Time in Patent Office: 1,113 Days
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

Claims

1. A device structure for a nitride semiconductor transistor comprising:

a substrate having a nitride semiconductor layer formed on a device area of the substrate, the nitride semiconductor layer defining a plurality of active regions for an array of islands of a multi-island transistor, the array of islands extending in first and second directions over the device area,

each of said active regions comprising a two dimensional electron gas (2DEG) region isolated from adjacent active regions by an intervening inactive region of the device area;

each island having a source electrode, a drain electrode and a gate electrode formed on a respective active region of the island, each source electrode having a plurality of source peninsulas, each drain electrode having a plurality of drain peninsulas, the source and drain peninsulas being interleaved and spaced apart over the active region of the island to define a channel region therebetween, the gate electrode being formed on the nitride semiconductor layer over the channel region and running between the source and drain peninsulas across the island;

each source electrode having a source contact area, each drain electrode having a drain contact area and each gate electrode having a gate contact area; and

the source, drain and gate electrodes of each island of the array of islands having an arrangement wherein each island is electrically isolated from the source, drain and gate electrodes of neighbouring islands in at least one of said first and second directions, and

wherein the source, drain and gate contact areas of each island provide for electrical probing and testing of individual islands for identification of defective islands and for selective isolation of a defective island from other islands of the array.

2. The device structure of claim 1 wherein the source, drain and gate electrode contact areas of individual islands each comprise a contact pad having at least a minimum size of at least 25 μ

m diameter required for electrical probing and testing for identification of defective islands.

3. The device structure of claim 2 wherein:

the array of islands comprises an n×

m matrix of n rows and m columns of islands.

4. The device structure of claim 3 wherein, for i=1 to n, the source contact areas and gate contact areas of the ith and i−

1th rows of islands are arranged in rows, positioned over inactive regions of the device area between the i−

1th and ith rows of islands; and

drain contact areas of the ith and i+1th rows of islands are arranged in rows, positioned over inactive regions of the device area between the ith and i+1th rows of islands.

5. The device structure of claim 3 wherein the transistor further comprises an overlying interconnect structure comprising at least one dielectric layer and at least one metallization layer providing:

a source interconnection interconnecting in parallel the source electrodes of sets of multiple islands;

a drain interconnection interconnecting in parallel the drain electrodes of sets of multiple islands; and

a gate interconnection interconnecting the gate electrodes of multiple islands to form a common gate.

6. The device structure of claim 5 wherein said source, drain and gate interconnections are provided selectively to respective source, drain and gate electrodes of islands, excluding defective islands, to provide electrical isolation of defective islands.

7. The device structure of claim 2, comprising defective islands, and further comprising a layer of electrically insulating material that is patterned to isolate at least one of the gate contact, source contact and drain contact of each defective island thereby providing electrical isolation of the defective islands before fabrication of an overlying interconnect structure for respective gate, source and drain interconnections.

8. The device structure of claim 1 wherein the array of islands comprises a matrix of rows and columns of islands,

the 2DEG region of each island is isolated from the 2DEG region of each neighbouring island by inactive regions of the substrate extending in the first and second directions between rows and columns of islands, and

in the first direction, except at edges of the array, each source electrode is positioned adjacent to a source electrode of a neighbouring island, and each drain electrode is adjacent to a drain electrode of a neighbouring island, for isolation between neighbouring islands in the first direction;

in the second direction, except at edges of the array, at least some source electrodes are positioned adjacent a source electrode of a neighbouring island, and at least some drain electrodes are positioned adjacent a drain electrode, for isolation between sets of neighbouring islands in the second direction; and

wherein the contact areas of each source electrode, each drain electrode and each gate electrode are located over the inactive region of the substrate extending between islands in the first direction.

9. The device structure of claim 8 wherein, in the second direction, except at edges of the array, each source electrode is positioned adjacent a source electrode of a neighbouring island, and each drain electrode is positioned adjacent a drain electrode for isolation between each neighbouring island in the second direction.

10. The device structure of claim 8 wherein, in the second direction, except at edges of the array, for a set of islands, a side of at least one source electrode is positioned adjacent a source electrode of a neighbouring island, and/or a side of at least one drain electrode is positioned adjacent a drain electrode for isolation between sets of neighbouring islands in the second direction.

11. The device structure of claim 8 wherein for each group of four islands, the source and drain electrodes are arranged to provide said isolation between each row of islands.

12. The device structure of claim 1, wherein the array of islands comprises a matrix of rows and columns of islands and wherein

in the first direction, the 2DEG region extends between neighbouring pairs of islands of a row, and in the second direction, the 2DEG region of each island is isolated from the 2DEG region of neighbouring islands of a column by inactive regions of the substrate extending between rows of islands;

in the first direction, except at edges of the array, each source electrode is positioned adjacent to a source electrode of a neighbouring island, and each drain electrode is adjacent to a drain electrode of a neighbouring island;

in the second direction, except at edges of the array, at least some source electrodes are positioned adjacent a source electrode of a neighbouring island, and at least some drain electrodes are positioned adjacent a drain electrode of a neighbouring island; and

wherein contact areas of each source electrode, each drain electrode and each gate electrode are located over the inactive region of the substrate between rows of islands.

13. The device structure of claim 12 wherein, the the rows and columns of islands are arranged as a repeating pattern of a group of four islands, wherein the source and drain electrodes are arranged to provide isolation between at least each row of islands.

14. The device structure of claim 13 wherein source electrodes of neighbouring cells in the first and second directions are coupled to form a common source electrode for each neighbouring pair of rows of islands.

15. The device structure of claim 14 wherein the source and drain electrodes are further arranged to provide an active region between each column of islands.

16. The device of claim 15 wherein source electrodes of adjacent islands in a row direction are interconnected to form a common source across at least part of the row.

17. The device structure of claim 14 wherein said contact areas to the respective source electrodes and drain electrodes are provided on promontories of each respective source and drain electrode, said promontories extending over the inactive region.

18. The device structure of claim 8 wherein said contact areas to the respective source electrodes and drain electrodes are provided on promontories of each respective source and drain electrode, said promontories being tapered and extending over the inactive region between rows of islands.

19. The device structure of claim 14 wherein, for a normally-on device, for each island, the contact area of the gate electrode is arranged over the inactive region in the vicinity of the source contact of the respective island.

20. The device structure of claim 8 comprising a centre-fed gate arrangement wherein respective gate contacts of each island pair in a first direction are centered over the inactive region between each island pair and a gate connection connecting a centre region of each island gate electrode to its respective gate contact pad.

21. The device of claim 8 wherein the array comprises a plurality of islands arranged as a repeating pattern of a building block of four islands.

22. The device of claim 8 wherein the array comprises a plurality of islands arranged as a repeating pattern of a building block of four islands, the four islands of the building block being arranged in a pattern having p2 mg symmetry.

23. The device of claim 5 wherein the gate interconnection comprises one or more gate straps extending in the first direction and interconnecting gate contacts of adjacent islands;

the source interconnection comprises one or more source straps extending in the first direction and interconnecting source electrodes of adjacent islands; and

the drain island interconnection comprises one or more drain straps extending in the first direction and interconnecting source electrodes of adjacent islands.

24. The device of claim 5 wherein the source, drain and gate interconnections comprise a metallization layer defining source super pads interconnecting each neighbouring pair of source contact areas and drain super pads interconnecting each neighbouring pair of drain contact areas, gate super pads interconnecting each neighbouring pair of gate contact areas, and

a metallization structure formed thereon comprising at least one insulating layer isolating source super pads and drain super pads and gate super pads from each other, an overlying conductive layer defining source, drain and gate straps, and conductive vias extending through the isolation layer to respective source, drain and gate super pads.

25. A method for testing and fabrication of a device structure for a transistor, comprising the steps of:

providing the device structure of claim 1, probing and electrically testing islands of the array, identifying and/or mapping defective islands; and

selectively providing source, drain and gate electrical connections to islands other than said defective islands, thereby electrically isolating defective islands of the transistor.

28. The device structure of claim 5, wherein said overlying interconnect structure comprises electrical connections formed on said respective contact areas of the source, drain and gate electrodes of non-defective islands, comprising any one of:

a) ball/bump interconnections;

b) via type interconnections;

c) conductive posts; and

d) a combination thereof.

29. The device structure of claim 14 comprising a centre-fed gate arrangement wherein respective gate contacts of each island pair in a first direction are centered over the inactive region between each island pair and a gate connection connecting a centre region of each island gate electrode to its respective gate contact pad.

26. A device structure for a nitride semiconductor diode comprising:

a substrate having a nitride semiconductor layer formed on a device area of the substrate and defining a plurality of active regions for an array of islands of a multi-island diode,

the array of islands extending in first and second directions over the device area,

each of said active regions comprising a two dimensional electron gas (2DEG) region isolated from adjacent active regions by an intervening inactive region of the device area;

each island having an anode electrode and a cathode electrode formed on a respective active region of the island, each anode electrode having a plurality of anode peninsulas, each cathode electrode having a plurality of cathode peninsulas, the anode and cathode being interleaved and spaced apart over the active region of the island to define a channel region therebetween;

the anode and cathode electrodes of each island each having, respectively, an anode contact area and a cathode contact area; and

the anode and cathode electrodes of each island of the array of islands having an arrangement wherein at least one electrode of each island is electrically isolated from electrodes of neighbouring islands in at least one of said first and second directions, and

wherein the anode and cathode contact areas of each island provide for electrical probing and testing of individual islands for identification of defective islands and for selective isolation of a defective island from other islands of the array.

27. The device structure of claim 26, further comprising:

an overlying isolation layer providing contact openings only to contact areas of non-defective islands and isolating contact areas of defective islands;

an anode interconnection interconnecting the anode island electrodes in parallel;

a cathode interconnection interconnecting the cathode island electrodes in parallel; and

said anode and cathode interconnections thereby selectively connecting non-defective islands and providing electrical isolation of defective islands of the multi-island diode.