Approach to minimization of strain loss in strained fin field effect transistors
First Claim
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1. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:
- forming a strained vertical fin on a substrate;
forming a plurality of gate structures on the strained vertical fin;
forming an interlevel dielectric on the strained vertical fin;
forming a source/drain contact on the strained vertical fin adjacent to each of the plurality of gate structures;
selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure;
removing a portion of the strained vertical fin exposed by forming the trench; and
removing a portion of the substrate after removing the exposed portions of the strained vertical fin.
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Abstract
A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.
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Citations
14 Claims
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1. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:
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forming a strained vertical fin on a substrate; forming a plurality of gate structures on the strained vertical fin; forming an interlevel dielectric on the strained vertical fin; forming a source/drain contact on the strained vertical fin adjacent to each of the plurality of gate structures; selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure; removing a portion of the strained vertical fin exposed by forming the trench; and removing a portion of the substrate after removing the exposed portions of the strained vertical fin. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:
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forming a strained silicon-germanium (SiGe) vertical fin on a single crystal silicon substrate or a strained silicon (Si) vertical fin on a single crystal silicon-germanium substrate; forming three or more gate structures on the strained SiGe vertical fin or strained Si vertical fin; forming a gate spacer on each of the three or more gate structures; forming an interlevel dielectric on the gate spacers; forming four or more openings in the interlevel dielectric; forming four or more source/drain contacts in the interlevel dielectric on the strained SiGe vertical fin or strained Si vertical fin, where at least two of the source/drain contacts are between the gate spacers; selectively removing one or more of the source/drain contacts to form a trench in the interlevel dielectric; removing a portion of the strained SiGe vertical fin or strained Si vertical fin exposed by forming the trench; and removing a portion of the substrate after removing the exposed portions of the strained SiGe vertical fin or strained Si vertical fin. - View Dependent Claims (10, 11, 12, 13, 14)
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Specification