Approach to minimization of strain loss in strained fin field effect transistors

• US 9,818,875 B1
• Filed: 10/17/2016
• Issued: 11/14/2017
• Est. Priority Date: 10/17/2016
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bi, Zhenxing, Cheng, Kangguo, Li, Juntao, Xu, Peng
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US15/295,546
• Time in Patent Office: 393 Days
• Field of Search: 257401
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.

Claims

1. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:

forming a strained vertical fin on a substrate;

forming a plurality of gate structures on the strained vertical fin;

forming an interlevel dielectric on the strained vertical fin;

forming a source/drain contact on the strained vertical fin adjacent to each of the plurality of gate structures;

selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure;

removing a portion of the strained vertical fin exposed by forming the trench; and

removing a portion of the substrate after removing the exposed portions of the strained vertical fin.

2. The method of claim 1, further comprising forming an insulating liner in each trench and a trench fill on the insulating liner.

3. The method of claim 2, wherein the insulating liner is silicon nitride (SiN), a silicon oxynitride (SiON), a silicon carbonitride (SiCN), a silicon boronitride (SiBN), a silicon borocarbide (SiBC), a silicon boro carbonitride (SiBCN), a boron carbide (BC), a boron nitride (BN), or combinations thereof.

4. The method of claim 1, wherein the strained vertical fin is single crystal silicon-germanium (Site) and the substrate is single crystal silicon.

5. The method of claim 4, further comprising forming a plurality of gate spacers on the strained vertical fin, wherein each of the plurality of gate structures is formed within one of the gate spacers.

6. The method of claim 1, wherein the source/drain contacts are tungsten, titanium, cobalt, or a combination thereof.

7. The method of claim 6, wherein the source/drain contacts are removed using a selective dry etch.

8. The method of claim 1, wherein each trench is self-aligned with the adjacent gate structure after removal of the source/drain contacts by exposing a sidewall of the gate spacer between the trench and the adjacent gate structure.

9. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:

forming a strained silicon-germanium (SiGe) vertical fin on a single crystal silicon substrate or a strained silicon (Si) vertical fin on a single crystal silicon-germanium substrate;

forming three or more gate structures on the strained SiGe vertical fin or strained Si vertical fin;

forming a gate spacer on each of the three or more gate structures;

forming an interlevel dielectric on the gate spacers;

forming four or more openings in the interlevel dielectric;

forming four or more source/drain contacts in the interlevel dielectric on the strained SiGe vertical fin or strained Si vertical fin, where at least two of the source/drain contacts are between the gate spacers;

selectively removing one or more of the source/drain contacts to form a trench in the interlevel dielectric;

removing a portion of the strained SiGe vertical fin or strained Si vertical fin exposed by forming the trench; and

removing a portion of the substrate after removing the exposed portions of the strained SiGe vertical fin or strained Si vertical fin.

10. The method of claim 9, wherein the strained silicon-germanium (SiGe) vertical fin is epitaxially grown on the single crystal silicon substrate, or the strained silicon (Si) vertical fin is epitaxially grown on a single crystal silicon-germanium substrate.

11. The method of claim 9, wherein the height of the strained SiGe vertical fin and the germanium (Ge) concentration of the strained SiGe vertical fin are below a threshold value at which dislocations would appear in the vertical fin.

12. The method of claim 9, wherein removing an exposed portion of the strained SiGe vertical fin or strained Si vertical fin from the one or more trenches forms a plurality of strained SiGe vertical fin sections or strained Si vertical fin sections.

13. The method of claim 12, further comprising extending the one or more trenches into the substrate by a predetermined depth below the strained SiGe vertical fin or strained Si vertical fin.

14. The method of claim 13, further comprising forming an insulating liner in each of the one or more trenches.