Integrated circuits with optical flow computation circuitry
First Claim
1. An integrated circuit, comprising:
- a first storage circuit that stores image data from a current video frame;
a second storage circuit that stores image data from a previous video frame;
a plurality of column sum shift registers, wherein each column sum shift register receives input from at least the first storage circuit;
a plurality of square sum registers, wherein each square sum register receives input from a respective column sum shift register; and
an optical flow computation circuit that computes one pixel of output per clock cycle at least partly based on input from each square sum register of the plurality of square sum registers.
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Abstract
An integrated circuit with optical flow computation circuitry is provided. The optical flow computation circuitry may include a first image shift register for receiving pixel values from a current video frame, a second image shift register for receiving pixel values from a previous video frame, column shift registers for storing column sums of various gradient-based values, square sum registers for storing square sums generated at least partly based on the column sum values, and an associated computation circuit that constructs a gradient matrix based on values stored in the square sum registers and that computes a 2-dimensional optical flow vector based on an inverse of the gradient matrix and differences between the current and previous frames. Optical flow computing circuitry configured in this way may be capable of supporting dense optical flow calculation for at least one pixel per clock cycle while supporting large window sizes.
25 Citations
18 Claims
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1. An integrated circuit, comprising:
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a first storage circuit that stores image data from a current video frame; a second storage circuit that stores image data from a previous video frame; a plurality of column sum shift registers, wherein each column sum shift register receives input from at least the first storage circuit; a plurality of square sum registers, wherein each square sum register receives input from a respective column sum shift register; and an optical flow computation circuit that computes one pixel of output per clock cycle at least partly based on input from each square sum register of the plurality of square sum registers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 12, 13, 14, 15, 16, 17, 18)
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8. A method for computing an optical flow output on an integrated circuit, comprising:
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computing a first gradient matrix for a first pixel by computing column sum values based on horizontal and vertical gradient values associated with a column of pixels and by computing a square sum value based on the column sum values; and computing a second gradient matrix for a second pixel by reusing at least part of the first gradient matrix associated with the first pixel and by subtracting a left-most column sum in a window associated with the first pixel from the square sum value, wherein the second pixel is different than the first pixel. - View Dependent Claims (9, 10, 11)
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Specification