Critical path architect

• US 9,823,298 B2
• Filed: 08/12/2015
• Issued: 11/21/2017
• Est. Priority Date: 08/12/2015
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Balasubramanian, Satheesh, Shekhar, Shardendu, Dodrill, James Dennis, Suryanarayanan, Sainarayanan Karatholuvu
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US14/824,093
• Publication Number:
  US 20170045576A1
• Time in Patent Office: 832 Days
• Field of Search: 716115, 716114, 716113, 716112, 716108, 716122, 716136, 703 16
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.

Claims

1. A system, comprising:

a processor; and

memory having stored thereon instructions that, when executed by the processor, cause the processor to;

analyze timing data of an integrated circuit, wherein the timing data includes transition times for cells along paths of the integrated circuit;

identify instances of timing degradation for the cells along the paths of the integrated circuit in which an output transition time is higher than an input transition time;

recommend changes for the instances of the cells along the paths having timing degradation, wherein if a length of a path having timing degradation exceeds a first threshold value or a number of inverters or buffers succeeding the path having timing degradation exceeds a second threshold value, split the path into a resistance critical path or a capacitance critical path and assigning a non-default rule to the resistance critical path or the capacitance critical path;

generate at least one file for fabricating an integrated circuit in accordance with the recommended changes; and

fabricate, or cause to be fabricated, an integrated circuit in accordance with the at least one file.

2. The system of claim 1, wherein the cells comprise standard cells.

3. The system of claim 2, wherein the paths of the integrated circuit comprise a series of standard cells.

4. The system of claim 1, wherein the instructions to recommend changes for the instances of the cells along the paths having timing degradation comprise instructions to upsize the instances of the cells along the paths having timing degradation to decrease the output transition time to be equal to or less than the input transition time.

5. The system of claim 1, wherein the instructions to recommend changes for the instances of the cells along the paths having timing degradation comprise instructions to modify a threshold voltage of the instances of the cells along the paths having timing degradation to decrease the output transition time to be equal to or less than the input transition time.

6. The system of claim 1, wherein the instructions to identify instances of timing degradation comprise instructions to identify instances of route length along the paths of the integrated circuit that cause timing degradation.

7. The system of claim 6, wherein the instructions to recommend changes for the instances of the cells along the paths having timing degradation comprise instructions to increase a width of a wire trace along the paths of the integrated circuit that cause timing degradation.

8. The system of claim 6, wherein the instructions to recommend changes for the instances of the cells along the paths having timing degradation comprise instructions to increase spacing between wire traces along the paths of the integrated circuit that cause timing degradation.

9. The system of claim 1, wherein the instructions to identify instances of timing degradation comprise instructions to identify instances of cells along the paths of the integrated circuit in which the cells comprise multi-bit flip-flops.

10. The system of claim 9, wherein the instructions to recommend changes for the instances of the cells along the paths having timing degradation comprise instructions to debank or unbank the multi-bit flip-flops into individual flip-flops.

11. The system of claim 1, wherein the instructions to identify instances of timing degradation comprise instructions to identify one or more paths of the integrated circuit in which to assign a weighted priority for performance enhancement.

12. The system of claim 11, wherein the instructions to recommend changes for the instances of the cells along the paths having timing degradation comprise instructions to recommend changes for the paths based on the assigned weighted priority.

13. A non-transitory computer readable storage medium, the non-transitory computer readable storage medium having stored thereon instructions that, when executed by a processor, cause the processor to:

analyze timing data of an integrated circuit, wherein the timing data includes input and output transition times for cells along paths of the integrated circuit;

identify instances of the cells along the paths of the integrated circuit in which an output transition time is greater than an input transition time;

recommend changes for the instances of the cells along the paths having the output transition time greater than the input transition time, wherein if a length of a path having timing degradation exceeds a first threshold value or a number of inverters or buffers succeeding the path having timing degradation exceeds a second threshold value, split the path into a resistance critical path or a capacitance critical path and assigning a non-default rule to the resistance critical path or the capacitance critical path;

generate at least one file for fabricating an integrated circuit in accordance with the recommended changes; and

fabricate, or cause to be fabricated, an integrated circuit in accordance with the at least one file.

14. The computer readable storage medium of claim 13, wherein the instructions to recommend changes comprise instructions to:

upsize the instances of the cells along the paths to decrease the output transition time to be equal to or less than the input transition time;

or

modify a threshold voltage of the instances of the cells along the paths to decrease the output transition time to be equal to or less than the input transition time.

15. The computer readable storage medium of claim 13, wherein the instructions to recommend changes comprise instructions to:

increase a width of a wire trace along the paths of the integrated circuit that cause timing degradation;

or

increase spacing between wire traces along the paths of the integrated circuit that cause timing degradation.

16. The computer readable storage medium of claim 13, comprising instructions to:

identify instances of cells along the paths of the integrated circuit in which the cells comprise multi-bit flip-flops; and

debank or unbank the multi-bit flip-flops into individual flip-flops.

17. The computer readable storage medium of claim 13, comprising instructions to:

identify one or more paths of the integrated circuit in which to assign a weighted priority for performance enhancement; and

recommend changes for the paths based on the assigned weighted priority.

18. A method, comprising:

analyzing timing data of an integrated circuit, wherein the timing data includes input and output transition times for cells along paths of the integrated circuit;

identifying instances of the cells along the paths of the integrated circuit in which an output transition time is greater than an input transition time;

recommending changes for the instances of the cells along the paths having the output transition time greater than the input transition time, wherein recommending changes includes debanking or unbanking multi-bit flip-flops into individual flip-flops;

generating at least one file for fabricating an integrated circuit in accordance with the recommended changes; and

fabricating, or causing to be fabricated, an integrated circuit in accordance with the at least one file.

19. The method of claim 18, further comprising:

identifying one or more paths of the integrated circuit in which to assign a weighted priority for performance enhancement; and

recommending changes for the paths based on the assigned weighted priority.