Measuring internal signals of an integrated circuit

• US 9,823,306 B2
• Filed: 02/11/2016
• Issued: 11/21/2017
• Est. Priority Date: 02/11/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Murthy, Kushal D, Parmar, Manish, Tadeparthy, Preetam, Venkateswaran, Muthusubramanian
• Primary Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US15/042,132
• Publication Number:
  US 20170234926A1
• Time in Patent Office: 649 Days
• Field of Search: None
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

Claims

1. A method for testing an integrated circuit, the method comprising:

generating a plurality of internal signals within the integrated circuit (IC);

selecting a first internal signal from the plurality of internal signals in response to a command from an external test station;

coupling the first internal signal to a first external pin of the IC either directly or via a buffer circuit located within the IC in response to a command from the external test station; and

measuring the first internal signal by the external test station by monitoring the first external pin of the IC to produce a measured value;

further including calibrating the buffer circuit by;

providing a known calibration signal to a second external pin of the IC;

coupling the known calibration signal to the first external pin of the IC via the buffer circuit in response to a command from the external test station; and

measuring the known calibration signal after it is buffered by monitoring the first external pin of the IC by the external test station to produce a calibration value.

2. The method of claim 1, further including adjusting the measured value of the first internal signal using the calibration value.

3. The method of claim 1, in which a plurality of calibration signals are provided to the second external pin.

4. The method of claim 3, in which the plurality of calibration signals have amplitudes that range in value from a first supply voltage level of the IC to a second supply voltage level of the IC.

5. A method for testing an integrated circuit, the method comprising:

generating a plurality of internal signals within the integrated circuit (IC);

selecting a first internal signal from the plurality of internal signals in response to a command from an external test station;

coupling the first internal signal to a first external pin of the IC either directly or via a buffer circuit located within the IC in response to a command from the external test station; and

measuring the first internal signal by the external test station by monitoring the first external pin of the IC to produce a measured value;

further including;

determining a common mode of the first internal signal; and

selecting from among more than one buffer to couple the first internal signal to the first external test pin in accordance with the common mode of the first internal signal.

6. The method of claim 5, in which a first one of the buffers is a PMOS source follower, and in which a second one of the buffers is an NMOS source follower.

7. The device of claim 6, in which the PMOS source follower is selected for buffering signals having an amplitude in a range of approximately a threshold value to a ground reference value, and in which the NMOS source follower is selected for buffering signals having an amplitude in a range of approximately a threshold value to a supply reference value.