One-time programming in reprogrammable memory

• US 9,823,860 B2
• Filed: 03/14/2014
• Issued: 11/21/2017
• Est. Priority Date: 03/14/2014
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Vauclair, Marc, Teuwen, Philippe
• Primary Examiner(s): Tsui, Daniel
• Assistant Examiner(s): VILLANUEVA, LEANDRO R
• Application Number:
  US14/213,732
• Publication Number:
  US 20150261458A1
• Time in Patent Office: 1,348 Days
• Field of Search: None
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/0059 Security or protection circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

A portion of a reprogrammable storage device is used to implement permanent data storage. The storage device includes a plurality of electrically erasable memory elements and a controller. The plurality of electrically erasable memory elements are configured to store data. Each memory element is programmable a number of write cycles before reaching a write failure state. The controller is coupled to the plurality of memory elements. The controller includes a receiver and a write engine. The receiver receives an instruction to drive a selected memory element to the write failure state. The write engine repeatedly writes a data value, in a plurality of write operations, to the selected memory element until the write failure state of the selected memory element is established.

Claims

1. A storage device comprising:

a plurality of electrically erasable memory elements configured to store data, wherein each memory element is programmable a number of write cycles before reaching a write failure state; and

a controller coupled to the plurality of memory elements, wherein the controller comprises;

a receiver configured to receive an instruction to drive a selected memory element to the write failure state;

a write engine configured to perform a predetermined number of write operations to write a data value to the selected memory element that is an opposite of an initial data value stored in the selected memory element to switch the storage device out of a debug mode and to initiate a write operation to attempt to write a test data value to the selected memory element, wherein the data value comprises a non-zero sequence of at least three bits, and wherein the test data value is different from the data value; and

a comparator configured to generate a comparison result of a comparison of a stored data value of the selected memory element to the test data value, wherein the comparison result is indicative of whether the test data value is stored in the selected memory element, and wherein the write engine is further configured to perform a final set of additional write operations to attempt to write the data value to the selected memory element in response to a determination that the stored data value is not equal to the test data value.

2. The storage device of claim 1, wherein the write engine is further configured to perform additional write operations to write the data value to the selected memory element in response to a determination that the stored data value equals the test data value.

3. The storage device of claim 2, wherein the controller is further configured to control the write engine and the comparator to repeat:

the write operations to write the test data value;

the comparison; and

the additional write operations;

until the comparison result is indicative that the stored data value does not equal the test data value.

4. The storage device of claim 1, wherein the write engine is further configured to:

perform a first sequence of the write operations to repeatedly write the data value to the selected memory element, wherein the first sequence of the write operations comprises a number of write operations equal to or greater than a first threshold number of write cycles; and

perform a second sequence of the write operations to write the data value to the selected memory element in response to a determination that the selected memory element can store a newly written data value.

5. The storage device of claim 4, wherein the controller further comprises:

a read engine configured to read a stored data value from the selected memory element after each sequence of the write operations; and

wherein the write engine is further configured to repeat the second sequence of the write operations in response to a subsequent determination that the selected memory element can store another newly written data value.

6. The storage device of claim 5, wherein the controller further comprises:

a data value generator to generate an arbitrary data value;

wherein the write engine is further configured to write the arbitrary data value to the selected memory element prior to the read engine reading the stored data value; and

a comparator configured to compare the stored data value of the selected memory element to the arbitrary data value to determine if the arbitrary data value is stored in the selected memory element.

7. The storage device of claim 1, wherein the controller is further configured to manage a map of the plurality of memory elements, wherein the map designates blocks of the memory elements to drive to the write failure state for storage of fused data values that cannot be changed by subsequent write operations.

8. The storage device of claim 7, wherein the controller further comprises an override engine, wherein the override engine prevents wear leveling procedures for the blocks of the memory elements designated in the map for storage of the fused data values.

9. A method comprising:

receiving an instruction to drive a selected block of memory elements to a write failure state to permanently store a data value;

performing a predetermined number of write operations to write a data value to the selected block of memory elements that is an opposite of an initial data value stored in the selected memory element to switch the storage device out of a debug mode, wherein the data value comprises a non-zero sequence of at least three bits;

initiating a write operation to attempt to write a test data value to the selected block of memory elements, wherein the test data value is different from the data value;

generating a comparison result of a comparison of a stored data value of the selected block of memory elements to the test data value, wherein the comparison result is indicative of whether the test data value is stored in the selected block of memory elements; and

performing a final set of additional write operations to attempt to write the data value to the selected block of memory elements in response to a determination that the stored data value is not equal to the test data value.

10. The method of claim 9, wherein performing the plurality of repetitive write operations further comprises rewriting the data value to the selected block of memory elements until the write failure state is achieved for the selected block of memory elements.

11. The method of claim 9, further comprising:

determining that the stored data value is equal to the test data value; and

performing an additional sequence of write operations to attempt to write the data value to the selected block of memory elements to achieve the write failure mode of the selected block of memory elements.

12. The method of claim 9, further comprising reserving a portion of the plurality of electrically erasable memory elements for driving to the write failure state and storing data that cannot be changed by subsequent write operations.

13. The method of claim 9, further comprising preventing application of wear leveling techniques to the selected block of memory elements.

14. A system comprising:

a plurality of rewritable memory elements within a memory device, wherein at least some of the memory elements are designated for use in a state in which the designated memory elements cannot be rewritten; and

a controller coupled to the plurality of memory elements, wherein the controller comprises;

a read engine to read a stored data value from a block within the designated memory elements;

a write engine configured to perform a predetermined number of a write operations to write a data value to the block within the designated memory elements that is an opposite of an initial data value stored in the selected memory element to switch the storage device out of a debug mode and to initiate a write operation to attempt to write a test data value to the block within the designated memory elements, wherein the data value comprises a non-zero sequence of at least three bits, and wherein the test data value is different from the data value; and

a comparator configured to generate a comparison result of a comparison of a stored data value of the block within the designated memory elements to the test data value, wherein the comparison result is indicative of whether the test data value is stored in the block within the designated memory elements, and wherein the write engine is further configured to perform a final set of additional write operations to attempt to write the data value to the block within the designated memory elements in response to a determination that the stored data value is not equal to the test data value.

15. The system of claim 14, wherein the controller is further configured to store a designation of the block within the designated memory elements as storing a fused data value that cannot be changed by a subsequent write operation.