Systems and methods for throttling packet transmission in a scalable memory system protocol

• US 9,823,864 B2
• Filed: 05/28/2015
• Issued: 11/21/2017
• Est. Priority Date: 06/02/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pawlowski, J. Thomas
• Primary Examiner(s): Thier, Michael
• Assistant Examiner(s): Nowlin, Eric
• Application Number:
  US14/724,510
• Publication Number:
  US 20150350082A1
• Time in Patent Office: 908 Days
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0617 in relation to availability
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 : Single storage device
• CPC Class Codes: G06F 3/0679 : Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0683 : Plurality of storage devices
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H04L 1/189 : Transmission or retransmission of more than one copy of a message
• CPC Class Codes: H04L 47/12 : Avoiding congestion; Recovering from congestion
• CPC Class Codes: H04L 47/25 : with rate being modified by the source upon detecting a change of network conditions
• CPC Class Codes: H04L 47/52 : by attributing bandwidth to queues
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method may include transmitting, via a processor, a plurality of packets to a receiving component, such that the plurality of packets corresponds to a plurality of data operations configured to access a memory component. The plurality of packets is stored in a buffer of the receiving component upon receipt. The method may also include determining, via the processor, whether an available capacity of the buffer is less than a threshold, decreasing a transmission rate of the plurality of packets when the available capacity is less than the threshold.

Claims

1. A memory device comprising:

a memory component configured to store data;

a buffer;

a processor configured to execute one or more computer-executable instructions that cause the processor to;

receive a plurality of packets from a requesting component, wherein the plurality of packets corresponds to a plurality of data operations configured to access the memory component, and wherein the plurality of packets is stored in the buffer;

monitor an available capacity of the buffer;

determine whether the available capacity of the buffer is less than a threshold; and

send a message to the requesting component when the available capacity is less than the threshold, wherein the message comprises instructions for the requesting component to decrease a transmission rate of the plurality of packets based on a transaction window of each of the plurality of packets, wherein the transaction window comprises information indicating a type of memory component associated with a data operation of a respective packet of the plurality of packets.

2. The memory device of claim 1, wherein the threshold corresponds to 90% of a total capacity of the buffer.

3. The memory device of claim 1, wherein the instructions cause the requesting component to decrease the transmission rate according to a linear function.

4. The memory device of claim 3, wherein the transmission rate is directly related to the available capacity.

5. The memory device of claim 1, wherein the instructions cause the requesting component to decrease the transmission rate according to a non-linear function.

6. The memory device of claim 1, wherein the instructions cause the requesting component to decrease the transmission rate according to a step down function.

7. A system, comprising:

a requesting component;

a memory device comprising;

a buffer;

a processor configured to execute one or more computer-executable instructions that cause the processor to;

receive a plurality of packets from the requesting component, wherein the plurality of packets corresponds to a plurality of data operations configured to access the memory device, and wherein the plurality of packets is stored in the buffer;

monitor an available capacity of the buffer;

determine whether the available capacity of the buffer is less than a threshold; and

send a message to the requesting component when the available capacity is less than the threshold, wherein the message comprises instructions for the requesting component to decrease a transmission rate of the plurality of packets based on a transaction window of each of the plurality of packets, wherein the transaction window comprises information indicating a type of memory component associated with a data operation of a respective packet of the plurality of packets.

8. The system of claim 7, wherein the buffer is a first-in-first-out buffer.

9. The system of claim 7, wherein the processor is configured to send the message to the requesting component when the buffer is full.

10. The system of claim 7, wherein the processor is configured to send the message when an outstanding transaction count associated with a number of a portion of the plurality of packets stored in the buffer exceeds a first value.

11. The system of claim 10, wherein the processor is configured to receive the first value via input from a user of the system.

12. The system of claim 7, wherein the processor is configured to send the message when the transmission rate exceeds a first value.

13. The system of claim 12, wherein the processor is configured to receive the first value via input from a user of the system.

14. A method comprising:

transmitting, via a processor, a plurality of packets to a receiving component, wherein the plurality of packets corresponds to a plurality of data operations configured to access a memory component, and wherein the plurality of packets is stored in a buffer of the receiving component upon receipt; and

decreasing, via the processor, a transmission rate of the plurality of packets based upon receipt of a message from the receiving component, wherein the message comprises instructions to decrease a transmission rate of the plurality of packets based on a transaction window of each of the plurality of packets, wherein the transaction window comprises information indicating a type of memory component associated with a data operation of a respective packet of the plurality of packets, and wherein the receiving component is configured to generate the message when an available capacity of the buffer is less than a threshold.

15. The method of claim 14, wherein determining whether the available capacity is less than the threshold comprises:

receiving, via the processor, information regarding an expected packet processing rate for the receiving component; and

determining whether the transmission rate exceeds the expected packet processing rate; and

decreasing, via the processor, the transmission rate when the transmission rate exceeds the expected packet processing rate.

16. The method of claim 14, wherein the message requesting that the transmission rate of the plurality of packets be decreased is received when the transmission rate exceeds an expected packet processing rate by the receiving component.

17. The method of claim 14, wherein the transmission rate is decreased according to a linear function.

18. The method of claim 14, wherein the transmission rate is decreased according to a non-linear function.