Electronic fault detection unit
First Claim
1. An electronic fault detection unit comprisinga first register arranged to be written from a first software portion,a second register arranged to be written from a second software portion,a comparator circuit arranged todetect that both the first and second register have been written,verify a relationship between first data written to the first register and second data written to the second register, andsignal a fault upon said verification failing, anda timer circuit arranged tosignal a fault if said verification of the comparator circuit does not occur within a time limitwherein the timer circuit is arranged to start timing an interval upon writing of the first or second register, the time limit is reached upon the interval expiring, so that the timer signals the fault if the other one of the first register or the second register is not written within the interval.
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Accused Products
Abstract
An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit.
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Citations
20 Claims
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1. An electronic fault detection unit comprising
a first register arranged to be written from a first software portion, a second register arranged to be written from a second software portion, a comparator circuit arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing, and a timer circuit arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit wherein the timer circuit is arranged to start timing an interval upon writing of the first or second register, the time limit is reached upon the interval expiring, so that the timer signals the fault if the other one of the first register or the second register is not written within the interval.
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3. An electronic fault detection unit, comprising
a first register arranged to be written from a first software portion, a second register arranged to be written from a second software portion, a comparator circuit arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing, and a timer circuit arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit a configuration register arranged to configure the comparator circuit for one of multiple relationships in dependence upon configuration data written to the configuration register, the multiple relationships including at least: -
an equality relationship, wherein the comparator circuit is arranged to verify that the first data equals the second data, a first inequality relationship, wherein the comparator circuit is arranged to verify that the first data is less than the second data. - View Dependent Claims (4, 5, 16, 17, 18, 19, 20)
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14. A computer implemented fault detection method for use with a data processing device comprising a first fault detection unit and a second fault detection unit,
in a first software portion: -
performing a first computation resulting in a first computation result, and writing the first computation result to a first register of a first fault detection unit of the data processing device, the first fault detection unit being configured for a first inequality relationship, wherein a comparator circuit of the first fault detection unit is arranged to verify that a first data written to the first register of the first fault detection unit is less than a second data written to a second register of the first fault detection unit adding a threshold value to the first computation result, and to write the result to a first register of a second fault detection unit of the data processing device, the second fault detection unit being configured for a second inequality relationship, wherein a comparator circuit of the second fault detection unit is arranged to verify that a first data written to the first register of the second fault detection unit is more than a second data written to a second register of the second fault detection unit in a second software portion; performing a second computation resulting in a second computation result, and adding a threshold value to the second computation result, and to write the result to the second register of the first fault detection unit of the data processing device, writing the second computation result to the second register of the second fault detection unit of the data processing device.
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15. A non-transitory tangible computer readable storage medium comprising data loadable in a programmable data processing device, the data representing instructions executable by the programmable data processing device, said instructions comprising a first software portion and a second software portion,
the first software portion comprising one or more instructions arranged to perform a first computation resulting in a first computation result, and one or more instructions arranged to write the first computation result to a first register of a first fault detection unit of the data processing device, the first fault detection unit being configured for a first inequality relationship, wherein a comparator circuit of the first fault detection unit is arranged to verify that a first data written to the first register of the first fault detection unit is less than a second data written to the second register of the first fault detection unit one or more instructions arranged to add a threshold value to the first computation result, and to write the result to a first register of a second fault detection unit of the data processing device, the second fault detection unit being configured for a second inequality relationship, wherein a comparator circuit of the second fault detection unit is arranged to verify that a first data written to the first register of the second fault detection unit is more than a second data written to the second register of the second fault detection unit the second software portion comprising one or more instructions arranged to perform a second computation resulting in a second computation result, and one or more instructions arranged to add a threshold value to the second computation result, and to write the result to the second register of the first fault detection unit of the data processing device, one or more instructions arranged to write the second computation result to the second register of the second fault detection unit of the data processing device.
Specification