Memory node error correction

• US 9,823,986 B2
• Filed: 04/30/2013
• Issued: 11/21/2017
• Est. Priority Date: 04/30/2013
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Li, Sheng, Jouppi, Norman Paul, Faraboschi, Paolo, Yoon, Doe Hyun, Barron, Dwight L.
• Primary Examiner(s): Ehne, Charles
• Application Number:
  US14/786,615
• Publication Number:
  US 20160085653A1
• Time in Patent Office: 1,666 Days
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/2094 Redundant storage or storage space G06F11/2056 takes precedence
• CPC Class Codes: G06F 2201/805 Real-time
• CPC Class Codes: G06F 2201/85 Active fault masking without idle spares active fault masking without idle spare hardware where processing functionality is redundant G06F11/2035
• CPC Class Codes: G06F 2211/1059 Parity-single bit-RAID5, i.e. RAID 5 implementations

Abstract

According to an example, a resiliency group for a memory node in a memory network can provide error correction for a memory access in the memory node. The memory access may be received from a main memory controller of a processor connected to the memory network. The memory access may be executed by a memory controller of the memory node.

Claims

1. A memory network comprising:

memory nodes, wherein each memory node includes a memory and a memory controller logic;

inter-node links connecting the memory nodes with each other, wherein the memory controller logic of a memory node in the memory network is to receive a memory access request from a main memory controller of a processor connected to the memory network and detect an error in data for the memory access, and

a resiliency group for the memory node to provide error correction for the detected error, the resiliency group including at least one memory node in the memory network, wherein the memory network employs a tree structure and the resiliency group includes memory nodes in a parent-child relationship with the memory node receiving the memory access request.

2. The memory network of claim 1, wherein the resiliency group comprises a plurality of the memory nodes, including the memory node executing the memory access and another memory node connected to the memory node by one of the plurality of inter-node links.

3. The memory network of claim 2, wherein the plurality of memory nodes in the resiliency group are neighbors to the memory node for the memory access.

4. The memory network of claim 1, wherein an access group including a memory node for the memory access is to detect the error, and the resiliency group to correct the error includes multiple memory nodes.

5. The memory network of claim 1, wherein the memory controller logic of the memory node executing the memory access is to:

determine a source of the error;

determine whether the memory controller logic of the memory node executing the memory access is able to correct the error; and

correct the error in response to determining that the memory controller logic is able to correct the error.

6. The memory network of claim 5, wherein the memory controller logic of the memory node executing the memory access is to:

determine whether the resiliency group is able to correct the error in response to determining that the memory controller logic of the memory node is unable to correct the error; and

communicate with the resiliency group to correct the error in response to determining that the resiliency group is able to correct the error.

7. The memory network of claim 1, wherein a number of memory nodes in the resiliency group is determined based on performance, resiliency, and storage overhead.

8. The memory network of claim 1, wherein the memory controller logic in the memory node decomposes the memory access request into a group of read or write commands to be executed by the resiliency group.

9. The memory network of claim 8, wherein the memory node has a redundant memory node in the network and the memory node and the redundant memory node share a state of the execution of the group of read or write commands.

10. The memory network of claim 1, wherein a memory node in the memory network is to determine whether a lane in one of the inter-node links or an entire inter-node link failed, and to utilize another lane in the inter-node link or a different inter-node link in response to detecting the failure.

11. A memory node comprising:

a stacked memory including a plurality of memory layers;

a base logic layer including memory controller logic to perform memory accesses on the stacked memory, wherein the memory controller logic decomposes a memory access request into a group of read or write commands to be executed by a resiliency group for the memory node, the resiliency group to provide error correction for a detected error; and

vias connected to the plurality of layers to the base logic layer, wherein the base logic layer is to determine Reed-Solomon (RS) symbols for each memory bank or subarray in a different layer and a different vertical slice of the stacked memory, and each RS symbol provides error correction for the memory bank or subarray.

12. The memory mode of claim 11, wherein the memory controller logic is to detect an error for a memory access in the stacked memory, and to correct the error using at least one of the RS symbols.

15. The memory node of claim 12, wherein the memory node has a redundant memory node in the network and the memory node and the redundant memory node share a state of the execution of the group of read or write commands.

13. A method comprising:

determining a resiliency group of a memory node based on performance, resiliency, and storage overhead;

receiving a memory access request from a main memory controller of a processor at the memory node, wherein the memory node includes memory controller logic and memory;

executing the memory access in the memory by the memory controller of the memory node;

detecting an error of the memory access by the memory controller logic; and

correcting the error by the memory controller logic or correcting the error by the resiliency group of the memory node.

14. The method of claim 13, further comprising correcting the error by the resiliency group in response to the memory controller logic being unable to correct the error without the resiliency group.