Cache memory sharing in a multi-core processor (MCP)

• US 9,824,008 B2
• Filed: 11/21/2008
• Issued: 11/21/2017
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Kyndryl Incorporated
• Original Assignee: International Business Machines Corporation
• Inventors: Duvalsaint, Karl J., Kim, Daeik, Kim, Moon J.
• Primary Examiner(s): Yi, David X
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US12/275,552
• Publication Number:
  US 20100131716A1
• Time in Patent Office: 3,287 Days
• Field of Search: 711130, 711118, 711148, 709213
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc

Abstract

This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

Claims

1. A shared cache memory system, comprising:

a main controller;

a first memory unit mounted on a bus;

a first cache manager coupled to the first memory unit;

a first set of sub-memory units coupled to the first cache manager;

a first set of sub-processing elements coupled to the first set of sub-memory units; and

a second cache manager coupled to an input and an output of a second memory unit mounted on the bus, the first cache manager;

receiving instructions to mount the first set of sub-memory units to the second memory unit, responsive to a diagnosis on the first memory unit by the main controller, from the main controller in response to a cache miss at the first set of sub-memory units;

receiving a request for memory content originating from the first set of sub-processing elements;

isolating the first memory unit from the first set of sub-memory units and the first set of sub-processing elements by;

wrapping an input and an output of the first memory unit;

bypassing the first memory unit;

configuring mounting of the first cache manager based on the received mounting instructions; and

arranging the input and the output of the first memory unit to allow sharing to the second memory unit of requests made to the first memory unit; and

sharing the request for memory content to the input of the second memory unit via the second cache manager to enable the second memory unit to function as a next-level higher cache to the first memory unit in the case that the first set of sub-memory units experience a cache miss, the first memory unit exhibits a yield below a predetermined threshold, and the first set of sub-memory units and the first set of sub-processing elements are operational,

wherein the main controller is coupled at a top of a hierarchy on the bus and in communication with the first and second cache managers and the second cache manager directs the request to the input of the second memory unit to enable a search of the second memory unit and a second set of sub-memory units coupled to the second memory unit.

2. The shared cache memory system of claim 1, the first memory unit and the second memory unit comprising virtualized cache memory units.

3. The shared cache memory system of claim 1, the second cache manager being further operable to receive an additional request, and share the additional request to at least one of the following:

the first memory unit;

or a third memory unit.

4. The shared cache memory system of claim 1, a second set of sub-processing elements being coupled to the second set of sub-memory units.

5. The shared cache memory system of claim 1, the bus being coupled to the main controller.

6. The shared cache memory system of claim 1, the first cache manager further sharing the request when the first memory unit is inoperable.

7. The shared cache memory system of claim 1, the first cache manager being coupled to an input and an output of the first memory unit.

19. The shared cache memory system of claim 1, the first and second cache managers having a status stored in a memory of the first and second cache managers.

20. The shared cache memory system of claim 1, the first cache manager performing the following cache operation steps:

wrapping an input and an output of the first memory unit;

configuring bypassing of the first memory unit;

configuring mounting information for the first set of sub-memory units; and

arranging input and output for the first set of sub-memory units for sharing.

8. A shared cache memory system, comprising:

a first cache memory unit mounted on a bus;

a first cache manager coupled to an input and an output of the first cache memory unit;

a first set of sub-cache memory units coupled to the first cache manager;

a second cache memory unit mounted on the bus;

a second cache manager coupled to an input and an output of the second cache memory unit; and

a second set of sub-cache memory units coupled to the second cache manager, the first cache manager;

receiving instructions to mount the first set of sub-cache memory units to the second cache memory unit, responsive to a diagnosis on the first cache memory unit by a main controller, from the main controller in response to a cache miss at the first set of sub-cache memory units;

receiving a request for memory content originating from a first set of sub-processing elements;

isolating the first cache memory unit from the first set of sub-cache memory units by;

wrapping an input and an output of the first cache memory unit;

bypassing the first cache memory unit;

configuring mounting of the first cache manager based on the received mounting instructions; and

arranging the input and the output of the first cache memory unit to allow sharing to the second cache memory unit of requests made to the first cache memory unit; and

sharing the request for memory content with the input of the second cache memory unit via the second cache manager to enable the second cache memory unit to function as a next-level higher cache to the first cache memory unit in the case that the first set of sub-cache memory units experience a cache miss, the first cache memory unit exhibits a yield below a predetermined threshold, and the first cache memory unit is coupled to an operational first set of sub-cache memory units,

wherein the main controller is coupled at a top of a hierarchy on the bus and in communication with the first and second cache managers and the request is received from the second cache manager at an input of the second cache memory unit and the second set of sub-cache memory units.

9. The shared cache memory system of claim 8, further comprising a first set of sub-processing elements coupled to the first set of sub-cache memory units.

10. The shared cache memory system of claim 8, further comprising a second set of sub-processing elements coupled to the second set of sub-cache memory units.

11. The shared cache memory system of claim 8, the bus being coupled to the main controller.

12. A cache memory sharing method, comprising:

receiving a first request on a first cache manager, the first cache manager being coupled to a first memory unit, the first memory unit being coupled to a bus;

receiving instructions to mount a first set of sub-cache memory units to a second cache memory unit, responsive to a diagnosis on the first memory unit by a main controller, from the main controller in response to a cache miss at the first set of sub-memory units coupled to the first cache manager;

isolating the first memory unit from the first set of sub-memory units by;

wrapping an input and an output of the first memory unit;

bypassing the first memory unit;

configuring mounting of the first cache manager based on the received mounting instructions; and

arranging the input and the output of the first memory unit to allow sharing to the second memory unit of requests made to the first memory unit; and

sharing the request with the second memory unit by sending the request to a second cache manager in the case that a first set of sub-processing elements coupled to the first memory unit experiences a cache miss, the first memory unit exhibits a yield below a predetermined threshold, and the first set of sub-processing elements are operational,

wherein the main controller is coupled at a top of a hierarchy on the bus and in communication with the first and second cache managers and the request is received from the second cache manager at an input of the second memory unit and a second set of sub-cache memory units, the second cache manager being coupled to the second memory unit, the second memory unit being coupled to the bus, and the bus being coupled to the main controller.

13. The cache memory sharing method of claim 12, the first request being received from the first set of sub-memory units coupled to the first memory unit.

14. The cache memory sharing method of claim 12, further comprising:

receiving a second request on the second cache manager; and

sharing the second request by sending the second request from the second cache manager to at least one of the following;

the first cache manager;

or a third cache manager.

15. The cache memory sharing method of claim 13, the second request being received from a second set of sub-memory units coupled to the second memory unit.

16. The cache memory sharing method of claim 15, the first memory unit, the first set of sub-memory units, the second memory unit, and the second set of sub-memory units being cache memory units.

17. The cache memory sharing method of claim 12, further comprising sending a response to the first request from the second memory unit to an originator of the request.

18. The cache memory sharing method of claim 17, the response being sent via the second cache manager.