Memory systems with multiple modules supporting simultaneous access responsive to common memory commands

• US 9,824,036 B2
• Filed: 05/04/2015
• Issued: 11/21/2017
• Est. Priority Date: 02/28/2001
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Stark, Donald C., Ware, Frederick A., Tsern, Ely K., Hampel, Craig E.
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US14/702,995
• Publication Number:
  US 20150234754A1
• Time in Patent Office: 932 Days
• Field of Search: None
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1087 : Data input latches
• CPC Class Codes: G11C 8/06 : Address interface arrangements, e.g. address buffers
• CPC Class Codes: H05K 1/117 : Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 1/14 : Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 2201/09954 : More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
• CPC Class Codes: H05K 2201/10189 : Non-printed connector
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described are memory systems in which a memory controller issues commands and addresses to multiple memory modules that collectively support each read and write transactions. A common set of control signal lines from the controller communicates the same command and address signals to the modules. For write commands, the controller sends subsets of write data to each module over a respective subset of data lines. For read commands, each module responds with a subset of the requested data over the respective subset of data lines. The memory modules can be width configurable so that a single full-width module can connect to both subsets of data lines to convey full-width data, or two half-width modules can connect one each to the subsets of data lines.

Claims

1. A system comprising:

a controller to communicate data of a full data width;

first and second memory modules including first and second sets of memory devices, respectively;

a set of data lines coupled to the controller to communicate the data of the full data width, the set of data lines having a first subset of data lines connecting the controller to only one of the first and second memory modules and a second subset of data lines connecting the controller to only the other one of the first and second memory modules, the first subset of data lines non-overlapping with the second subset of data lines; and

a set of control lines that extends from the controller to both of the first memory module and the second memory module.

2. The system of claim 1, the first memory module including a mode register to store a memory-width configuration value.

3. The system of claim 2, wherein the first subset of data lines includes a number of data lines, the memory-width configuration value setting the first memory module to a narrow data width of the number of data lines.

4. The system of claim 1, further comprising at least one module connector to receive the first and second memory modules, the at least one module connector including a first data contact group coupled to the first subset of data lines, a second data contact group coupled to the second subset of data lines, and multiple control contact groups each coupled to the set of control lines.

5. The system of claim 4, wherein the set of control lines forks to convey control signals from the controller to the multiple control contact groups.

6. The system of claim 1, further comprising:

a first module connector to receive the first memory module and including a first data contact group coupled to the first subset of data lines;

a second module connector to receive the second memory module and including a second data contact group coupled to the second subset of data lines; and

a third subset of data lines extending between the first module connector and the second module connector.

7. A memory system comprising:

a controller to communicate full-width data;

a first memory module including a first memory device;

a second memory module including a second memory device;

a first data signal line set extending from the controller to the first memory module and detached from the second memory module, the first data signal line set to convey a first fraction of the full-width data;

a second data signal line set extending from the controller to the second memory module and detached from the first memory module, the second data signal line set to convey a second fraction of the full-width data; and

a control signal line set extending from the controller to both the first memory module and the second memory module.

8. The memory system of claim 7, wherein the first data signal line set includes a number of data signal lines and the second data signal line set includes the number of the data signal lines.

9. The memory system of claim 8, the first memory module including a mode register to a memory-width configuration value.

10. The memory system of claim 9, the memory-width configuration value setting the first memory module to a narrow data width of the number of data signal lines or to a wide data width of twice the number of the data signal lines.

11. The memory system of claim 7, further comprising at least one module connector to receive the first memory module and the second memory module, the at least one module connector including a first data contact group coupled to the first data signal line set, a second data contact group coupled to the second data signal line set, and multiple control contact groups coupled to the control signal line set.

12. The memory system of claim 11, wherein the control signal line set is split to convey control signals from the controller to the multiple control contact groups.

13. The memory system of claim 7, the first memory module including a cross-bar switch coupled to the first data signal lines.

14. The memory system of claim 13, the cross-bar switch being configurable to convey data of a first data width or a second data width.

15. The memory system of claim 7, further comprising:

a first module connector to receive the first memory module and including a first data contact group coupled to the first data signal line set;

a second module connector to receive the second memory module and including a second data contact group coupled to the second data signal line set; and

a third data signal line set extending between the first module connector and the second module connector.

16. A memory system comprising:

a memory controller to issue commands and addresses;

a first memory module to store first data;

a second memory module to store second data;

a control signal line set extending from the memory controller to both the first memory module and the second memory module, the control signal line set to convey the commands and addresses to both the first memory module and the second memory module;

a first data signal line set extending from the memory controller to the first memory module, the first data signal line set to convey the first data to the memory controller; and

a second data signal line set extending from the memory controller to the second memory module, the second data signal line set to convey the second data to the memory controller;

wherein the commands and addresses include a read command and associated read address, and wherein, responsive to the read command, the first memory module conveys some of the first data to the memory controller via the first data signal line set and the second memory module conveys some of the second data to the memory controller via the second data signal line set.

17. The memory system of claim 16, the first memory module including a mode register to a memory-width configuration value.

18. The memory system of claim 17, wherein the first data signal line set includes a number of data signal lines, the memory-width configuration value setting the first memory module to a narrow data width of the number.

19. The memory system of claim 18, the memory-width configuration value alternatively setting the first memory module to a wide data width greater than the number.

20. The memory system of claim 16, further comprising at least one module connector to receive the first memory module and the second memory module, the at least one module connector including a first data contact group coupled to the first data signal line set, a second data contact group coupled to the second data signal line set, and multiple control contact groups coupled to the control signal line set.

21. The memory system of claim 20, wherein the control signal line set is split to convey control signals from the memory controller to the multiple control contact groups.

22. The memory system of claim 16, further comprising:

a first module connector to receive the first memory module and including a first data contact group coupled to the first data signal line set;

a second module connector to receive the second memory module and including a second data contact group coupled to the second data signal line set; and

a third data signal line set extending between the first module connector and the second module connector, the third data signal line set to communicate third data between the first module connector and the second module connector in a single-module configuration of the memory system.