Method, apparatus and instructions for parallel data conversions

• US 9,824,061 B2
• Filed: 12/28/2016
• Issued: 11/21/2017
• Est. Priority Date: 09/08/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ramanujam, Gopalan
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US15/392,413
• Publication Number:
  US 20170109319A1
• Time in Patent Office: 328 Days
• Field of Search: 708204, 708550-553
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming

Abstract

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Claims

1. A system comprising:

at least one reduced instruction set computer (RISC) processor; and

a memory controller to couple the RISC processor to a system memory,

the RISC processor comprising;

a register file, within the RISC processor, including a first packed data register and a second packed data register;

a register renamer within the RISC processor;

a decoder, within the RISC processor, to decode instructions, the instructions to include a first instruction;

a scheduler, within the RISC processor, to queue operations that correspond to the instructions for execution; and

execution logic, within the RISC processor, coupled to the decoder, the register renamer, and the scheduler, the execution logic to perform out-of-order execution of at least some of the instructions;

wherein, responsive to a decode of the first instruction by the decoder, the execution logic is to convert a first plurality of packed signed data elements that are to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated;

the first plurality of packed signed data elements to include floating point data elements and the second plurality of packed unsigned data elements to include integer data elements;

at least one of the first plurality of packed signed data elements to have a first number of bits, at least one of the second plurality of packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits.

2. The system as in claim 1, wherein the first number of bits is 64 and the second number of bits is 32.

3. The system as in claim 1, wherein said one or more of the second plurality of packed unsigned data elements is to be saturated if a condition is satisfied.

4. A system comprising:

at least one reduced instruction set computer (RISC) processor; and

a memory controller to couple the RISC processor to a system memory,

the RISC processor comprising;

a register file, within the RISC processor, including a first packed data register and a second packed data register;

a register renamer within the RISC processor;

a decoder, within the RISC processor, to decode instructions, the instructions to include a first instruction;

a scheduler, within the RISC processor, to queue operations that correspond to the instructions for execution; and

execution unit, within the RISC processor, coupled to the decoder, the register renamer, and the scheduler, the execution unit to perform out-of-order execution of at least some of the instructions;

wherein, responsive to a decode of the first instruction by the decoder, the execution unit is to convert a first plurality of packed signed data elements that are to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated;

the first plurality of packed signed data elements to be floating point data elements and the second plurality of packed unsigned data elements to be integer data elements;

each of the first plurality of packed signed data elements to have a first number of bits, each of the second plurality of packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits.

5. The system as in claim 4, wherein the first number of bits is 64 and the second number of bits is 32.

6. The system as in claim 4, wherein said one or more of the second plurality of packed unsigned data elements is to be saturated if a condition is satisfied.

7. A machine readable medium storing instructions including a first instruction, the first instruction, if performed by a machine, is to cause the machine to perform operations comprising to:

decode the first instruction with a decoder within a reduced instruction set computer (RISC) processor of the machine;

access a first plurality of packed signed data elements that are to be stored in a first packed data register of a register file within the RISC processor;

rename registers with a register renamer within the RISC processor;

queue one or more operations that correspond to the first instruction for execution with a scheduler within the RISC processor; and

perform out-of-order execution of the first instruction with execution logic within the RISC processor, responsive to the decode of the first instruction by the decoder, including to convert the first plurality of packed signed data elements to a second plurality of packed unsigned data elements, to saturate one or more of the second plurality of packed unsigned data elements, and to store the second plurality of packed unsigned data elements in a second packed data register of the register file within the RISC processor,

wherein the first plurality of packed signed data elements are to include floating point data elements and the second plurality of packed unsigned data elements are to include integer data elements, and

wherein at least one of the first plurality of packed signed data elements is to have a first number of bits, at least one of the second plurality of packed unsigned data elements is to have a second number of bits, and the second number of bits is to be one half the first number of bits.

8. The machine readable medium of claim 7, wherein the instructions, if performed by the machine, are to cause the machine to perform operations comprising to use a memory controller to access data in a system memory.

9. The machine readable medium of claim 7, wherein the first number of bits is 64 and the second number of bits is 32.

10. The machine readable medium of claim 7, wherein the first instruction, if performed by the machine, is to cause the machine to perform operations comprising to saturate said one or more of the second plurality of packed unsigned data elements if a condition is satisfied.

11. The machine readable medium of claim 7, wherein the machine readable medium comprises a memory.

12. The machine readable medium of claim 7, wherein the machine readable medium comprises one of a magnetic storage disc and an optical storage disc.