Method, apparatus and instructions for parallel data conversions
First Claim
Patent Images
1. A system comprising:
- at least one reduced instruction set computer (RISC) processor; and
a memory controller integrated with the RISC processor, the memory controller to couple the RISC processor to a main memory,the RISC processor comprising;
a decoder to decode an instruction; and
execution logic to perform operations specified by the instruction;
wherein, to perform the operations, the execution logic is to expand and store M sub-elements of a first element of a packed data as a plurality of elements in a destination packed data storage location; and
wherein an element bit-width of the plurality of elements is greater than a sub-element bit-width of the M sub-elements.
0 Assignments
0 Petitions
Accused Products
Abstract
Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.
15 Citations
21 Claims
-
1. A system comprising:
-
at least one reduced instruction set computer (RISC) processor; and a memory controller integrated with the RISC processor, the memory controller to couple the RISC processor to a main memory, the RISC processor comprising; a decoder to decode an instruction; and execution logic to perform operations specified by the instruction; wherein, to perform the operations, the execution logic is to expand and store M sub-elements of a first element of a packed data as a plurality of elements in a destination packed data storage location; and wherein an element bit-width of the plurality of elements is greater than a sub-element bit-width of the M sub-elements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A system comprising:
-
at least one reduced instruction set computer (RISC) processor; and a memory controller integrated with the RISC processor, the memory controller to couple the RISC processor to a main memory, the RISC processor comprising; a decoder to decode an instruction; and an execution unit coupled with the decoder to perform operations specified by the instruction; wherein, to perform the operations, the execution unit is to expand and store M sub-elements of a first element of a packed data as a plurality of elements in a destination packed data storage location; and wherein an element bit-width of the plurality of elements is greater than a sub-element bit-width of the M sub-elements. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
-
-
17. A machine readable medium storing instructions including a first instruction, the first instruction, if performed by a machine, is to cause the machine to perform operations comprising to:
-
decode the first instruction with a decoder of a reduced instruction set computer (RISC) processor of the machine; perform operations specified by the first instruction with execution logic of the RISC processor, wherein, to perform the operations, the execution logic is to expand and store M sub-elements of a first element of a packed data as a plurality of elements in a destination packed data storage location of the RISC processor, wherein an element bit-width of the plurality of elements is to be greater than a sub-element bit-width of the M sub-elements. - View Dependent Claims (18, 19, 20, 21)
-
Specification