Method, apparatus and instructions for parallel data conversions

• US 9,824,063 B2
• Filed: 12/28/2016
• Issued: 11/21/2017
• Est. Priority Date: 09/08/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ramanujam, Gopalan
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US15/392,503
• Publication Number:
  US 20170109321A1
• Time in Patent Office: 328 Days
• Field of Search: 708204, 708550-553
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming

Abstract

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Claims

1. A system comprising:

at least one reduced instruction set computer (RISC) processor;

a memory controller integrated with the RISC processor; and

a network interface, the network interface coupled to the RISC processor to enable the RISC processor to send and receive data via a network,

wherein the RISC processor comprises;

a decoder to decode an instruction; and

execution logic to perform operations specified by the instruction;

wherein, to perform the operations, the execution logic is to expand and store M sub-elements of a first element of a packed data as a plurality of elements in a destination packed data storage location;

wherein an element bit-width of the plurality of elements is greater than a sub-element bit-width of the M sub-elements.

2. The system of claim 1, further comprising a graphics interface coupled to the RISC processor to receive commands and data from the RISC processor.

3. The system of claim 2, wherein the graphics interface comprises a frame buffer to store image data.

4. The system of claim 3, further comprising a display unit coupled to the frame buffer to display the image data.

5. The system of claim 1, further comprising a main memory, and wherein the memory controller is to couple the RISC processor to the main memory.

6. The system of claim 5, further comprising a graphics interface coupled to the RISC processor to receive commands and data from the RISC processor.

7. The system of claim 6, wherein the graphics interface comprises a frame buffer to store image data.

8. A system comprising:

at least one reduced instruction set computer (RISC) processor;

a memory controller integrated with the RISC processor; and

a network interface, the network interface coupled to the RISC processor,

wherein the RISC processor comprises;

a decoder to decode an instruction; and

an execution unit coupled with the decoder to perform operations specified by the instruction;

wherein, to perform the operations, the execution unit is to expand and store M sub-elements of a first element of a packed data as a plurality of elements in a destination packed data storage location;

wherein an element bit-width of the plurality of elements is greater than a sub-element bit-width of the M sub-elements.

9. The system of claim 8, further comprising a graphics interface coupled to the RISC processor to receive commands and data from the RISC processor.

10. The system of claim 9, wherein the graphics interface comprises a frame buffer to store image data.

11. The system of claim 10, further comprising a display unit coupled to the frame buffer to display the image data.

12. The system of claim 8, further comprising a main memory, and wherein the memory controller is to couple the RISC processor to the main memory.

13. The system of claim 12, further comprising a graphics interface coupled to the RISC processor to receive commands and data from the RISC processor.

14. The system of claim 13, wherein the graphics interface comprises a frame buffer to store image data.