Asynchronous pulse domain processor with adaptive circuit and reconfigurable routing

• US 9,824,311 B1
• Filed: 04/23/2014
• Issued: 11/21/2017
• Est. Priority Date: 04/23/2014
• Status: Active Grant

• Current Assignee: HRL Laboratories LLC (The Boeing Co.)
• Original Assignee: HRL Laboratories LLC (The Boeing Co.)
• Inventors: Cruz-Albrecht, Jose, Petre, Peter, White, Randall
• Primary Examiner(s): Holmes, Michael B
• Application Number:
  US14/259,314
• Time in Patent Office: 1,308 Days
• Field of Search: 706 25
• CPC Class Codes: G06N 3/044 Recurrent networks, e.g. Hopfield networks
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/08 Learning methods

Abstract

A liquid state machine pulse domain neural processor circuit comprising an asynchronous input filter circuit provided for, at any given time, receiving a series of analog input signals and generating in response a set of time-encoded values that depend on the series of analog input signals received at said given time and before said given time; and an asynchronous trainable readout map circuit for transforming at least a portion of said set of time encoded values into output signals.

Claims

1. A liquid state machine pulse domain neural processor circuit comprising:

an asynchronous input filter circuit provided for, at any given time, receiving a series of analog input signals and generating in response a set of time-encoded values that depend on the series of analog input signals received at said given time and before said given time; and

an asynchronous trainable readout map circuit for transforming at least a portion of said set of time encoded values into output signals;

wherein;

said generating a set of time-encoded values that depend on the series of analog input signals received at said given time and before said given time comprises receiving each analog input signal on a distinct input driver input port and outputting a corresponding pulse signal comprising a series of pulses having a predetermined frequency and having a duty cycle that depends on the value of the analog input signal.

2. The liquid state machine pulse domain neural processor circuit of claim 1 wherein the asynchronous input filter circuit comprises:

an input driver circuit arranged for said receiving each analog input signal on a distinct input driver input port and for said outputting, on a corresponding input driver output port, said pulse signal comprising a series of pulses having a predetermined frequency and having a duty cycle that depends on the value of the analog input signal;

a plurality of asynchronous nodes;

a plurality of asynchronous pulse domain processing cells having each an output port and a plurality of input ports;

a plurality of input port switches for controllably connecting any input port of any asynchronous pulse domain processing cell to any input driver output port;

a plurality of node switches for controllably connecting any asynchronous node to any input port of any asynchronous pulse domain processing cell; and

a plurality of output port switches for controllably connecting the output port of any asynchronous pulse domain processing cell to any asynchronous node.

3. The liquid state machine pulse domain neural processor circuit of claim 2 wherein the input port switches, node switches and output port switches are controllable such that at any given time the asynchronous input filter generates on the plurality of asynchronous nodes said set of time-encoded values that depends on the series of analog input signals received at said given time and before said given time.

4. The liquid state machine pulse domain neural processor circuit of claim 2, wherein each asynchronous pulse domain processing cell comprises:

a summing circuit having as many inputs as the asynchronous pulse domain processing cell has input ports;

a plurality of controllable weighing circuits having each an input coupled to an input port of the asynchronous pulse domain processing cell and an output coupled to an input of the summing circuit; and

a time encoder circuit having an input coupled to the output of the summing circuit.

5. The liquid state machine pulse domain neural processor circuit of claim 4, wherein the time encoder circuit comprises:

a two input summing integrator having an input coupled to the input of the time encoder circuit; and

a hysteresis quantizer having an input coupled to the output of the two input summing integrator and an output coupled to the output of the time encoder circuit;

wherein the output of the hysteresis quantizer is also connected to the second input of the two-input summing integrator.

6. The liquid state machine pulse domain neural processor circuit of claim 5, wherein the summing circuit of the asynchronous pulse domain processing cell is a lossy summing integrator.

7. The liquid state machine pulse domain neural processor circuit of claim 6, comprising a non linear limiter between the lossy summing integrator and the input of the time encoder circuit.

8. The liquid state machine pulse domain neural processor circuit of claim 4, wherein each controllable weighing circuit comprises a one-bit DAC arranged for receiving a pulse input signal having input signal levels and for generating an output signal identical to the input signal but having output signal levels that differ from the input signal levels by a programmable factor.

9. The liquid state machine pulse domain neural processor circuit of claim 6, wherein each a one-bit DAC has an adjustable gain controlled by a DAC receiving in input a digital value stored in a programmable memory.

10. The liquid state machine pulse domain neural processor circuit of claim 2 wherein the asynchronous trainable readout map circuit comprises:

a plurality of trainable asynchronous pulse domain processing cells having each an output port and a plurality of input ports associated each to a weighing port;

a plurality of adaptation cells associated each to a trainable asynchronous pulse domain processing cell;

each adaptation cell being provided for;

receiving the signal output on the output port of its associated trainable asynchronous pulse domain processing cell;

receiving a training target output signal; and

supplying weighing factors to the weighing ports of its associated trainable asynchronous pulse domain processing cell; and

a plurality of readout map switches for controllably connecting any asynchronous node of the input filter circuit to any input port of any trainable asynchronous pulse domain processing cell.

11. The liquid state machine pulse domain neural processor circuit of claim 10 wherein each adaptation cell is provided for generating weighing factors that depend on the integration, over a training time, of the difference between a low pass filtering of said signal output on the output port of its associated trainable asynchronous pulse domain processing cell and said training target output signal.

12. The liquid state machine pulse domain neural processor circuit of claim 10 wherein each trainable asynchronous pulse domain processing cell comprises:

a summing circuit having as many inputs as the trainable asynchronous pulse domain processing cell has input ports; and

a plurality of controllable weighing circuits having each an input coupled to an input port of the asynchronous pulse domain processing cell and an output coupled to an input of the summing circuit.

13. The liquid state machine pulse domain neural processor circuit of claim 12 wherein each trainable asynchronous pulse domain processing cell comprises a delay circuit between each input port and the input of the controllable weighing circuit that is coupled to the input port.

14. The liquid state machine pulse domain neural processor circuit of claim 12 wherein each adaptation cell comprises:

a low pass filter having an input connected to the output port of its associated trainable asynchronous pulse domain processing cell;

a subtractor circuit for subtracting the output of the low pass filter to a training target output signal received on a training signal input port;

a plurality of controllable weighing circuits having each an input coupled to an input port of its associated trainable asynchronous pulse domain processing cell, and a weighing control input coupled to the output of the subtractor circuit; and

a plurality of integrator circuits having each an input connected to the output of a controllable weighing circuit and an output connected to the weighing port associated to the input port to which the controllable weighing circuit is connected.

15. A method of processing a series of analog input signals;

the method comprising;

providing a liquid state machine pulse domain neural processor circuit having an asynchronous input filter circuit provided for, at any given time, receiving a series of analog input signals and generating in response a set of time-encoded values that depends on the series of analog input signals received at said given time and before said given time; and

an asynchronous trainable readout map circuit for transforming at least a portion of said set of time encoded values into output signals;

providing training analog input signals to the asynchronous input filter circuit as well as corresponding training output signals to the asynchronous trainable readout map circuit during a training period; and

after the training period, providing analog input signals to be processed to the asynchronous input filter circuit and outputting the corresponding output signals from the asynchronous trainable readout map circuit;

wherein;

said generating a set of time-encoded values that depend on the series of analog input signals received at said given time and before said given time comprises receiving each analog input signal on a distinct input driver input port and outputting a corresponding pulse signal comprising a series of pulses having a predetermined frequency and having a duty cycle that depends on the value of the analog input signal.

16. The method of claim 15, wherein providing analog input signals to be processed to the asynchronous input filter circuit comprises:

providing each of said corresponding pulse signal to at least one of a plurality of asynchronous pulse domain processing cells programmably interconnected for form a processing network.

17. The method of claim 16 wherein providing pulse signals to an asynchronous pulse domain processing cell comprises:

summing the pulse signals and generating an output pulse signal comprising a series of pulses having said predetermined frequency and having a duty cycle that depends on the value of the sum of the pulse signals.

18. The method of claim 17, further comprising assigning a predetermined weighing factor to each pulse signal prior to summing the pulse signals.

19. The method of claim 17, wherein summing the pulse signals comprises calculating a lossy summing integration of the pulse signals.

20. The method of claim 17, further comprising providing pulse signals output by said processing network to trainable asynchronous pulse domain processing cells, wherein said providing pulse signals to a trainable asynchronous pulse domain processing cell comprises:

generating an output signal comprising the sum of said pulse signals;

wherein said pulse signals are weighed with the integration over said training period of said pulse signals during said training period, said pulse signals during said training period being themselves weighed with the difference during said training period between a low pass filtering of the sum of said pulse signals and a training expected output value.

21. The method of claim 20, further comprising delaying each pulse signal prior to summing the pulse signals.