Systems and method for fast compensation programming of pixels in a display

• US 9,824,632 B2
• Filed: 05/16/2016
• Issued: 11/21/2017
• Est. Priority Date: 12/09/2008
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, Gholamreza, Azizi, Yaser, Ma, Maran Ran, Nathan, Arokia
• Primary Examiner(s): Tzeng, Fred
• Application Number:
  US15/155,820
• Publication Number:
  US 20160329017A1
• Time in Patent Office: 554 Days
• Field of Search: 345212
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2310/0259 with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/066 Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/023 using energy recovery or conservation
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: H05B 47/10 Controlling the light source
• CPC Class Codes: H05B 47/165 following a pre-assigned programmed sequence; Logic control [LC]

Abstract

Circuits for programming a circuit with decreased programming time are provided. Such circuits include a storage device such as a capacitor for storing display information and for ensuring a driving device such as a driving transistor drives a light emitting device according to the display information. To increase programming time, the pixel circuits may be pre-charged or a biasing current may be applied to charge and/or discharge a data line and/or the driving device. Aspects of the present disclosure allow for the biasing current to drain partially through the storage device to allow the portion of the biasing current applied to the driving device to remain small while the data line discharges. Furthermore, the present disclosure provides display architectures and operation schemes for display arranged in segments each including a plurality of pixel circuits.

Claims

1. A method of displaying an image on a display implemented in an interlacing mode, the display comprising a plurality of pixel circuits arranged in rows and columns, a first group of pixel circuits of the plurality of pixel circuits interlaced with a second group of pixel circuits of the plurality of pixel circuits, each of the pixel circuits including a light emitting device driven by a drive transistor according to programming information stored in a storage capacitor, the method comprising, during a single frame:

programming the first group of pixel circuits during a first programming time period during which none of the pixel circuits of the first group of pixel circuits emit light;

responsive to programming the first group of pixel circuits, during a first emission time period, emitting light from the first group of pixel circuits;

programming the second group of pixel circuits after programming of the first group of pixel circuits, during a second programming time period during which none of the pixel circuits of the second group of pixels circuits emit light; and

responsive to programming the second group of pixel circuits, during a second emission time period, emitting light from the second group of pixel circuits.

2. The method of claim 1, wherein the first group of pixel circuits and the second group of pixel circuits each comprise a plurality of rows of pixel circuits, each row of the first group of pixel circuits separated from at least one other row of the first group of pixel circuits by at least a row of the second group of pixel circuits, each row of the second group of pixel circuits separated from at least one other row of the second group of pixel circuits by at least a row of the first group of pixel circuits.

3. The method of claim 1, wherein the first group of pixel circuits are interlaced with the second group pixel circuits such that the first group of pixel circuits and the second group of pixel circuits are arranged in a checkerboard configuration with respect to one another.

4. The method of claim 1, further comprising, during the single frame:

idling the second group of pixel circuits during the first programming time period; and

idling the first group of pixel circuits during the second programming time period.

5. The method of claim 4, further comprising:

emitting light from the first group of pixel circuits during the second emission time period.

6. The method of claim 5, further comprising:

idling the first group of pixel circuits and the second group of pixel circuits during a first idling time period; and

upon expiry of the first idling time period emitting light from the first group of pixel circuits and the second group of pixel circuits during a third emission time period.

7. The method of claim 6 wherein programming the second group of pixel circuits is performed responsive to the expiry of the first emission time period, and wherein idling the first group of pixel circuits and the second group of pixel circuits is performed after expiry of the second emission time period.

8. The method of claim 6, wherein idling the first group of pixel circuits and the second group of pixel circuits is performed responsive to the expiry of the first emission time period.

9. The method of claim 6, wherein the first programming time period, the second programming time period, and the first idling time period are equal in duration.

10. The method of claim 6, wherein the idling includes turning off the display so that none of the pixel circuits emits light.

11. The method of claim 6, where a total emission duty cycle during the frame is 50%.

12. The method of claim 1, wherein programming the second group of pixel circuits is performed during the first emission time period.

13. The method of claim 1, wherein the first group of pixel circuits of the plurality of pixel circuits and the second group of pixel circuits of the plurality of pixel circuits are each interlaced with a third group of pixel circuits of the plurality of pixel circuits, the method further comprising, during the single frame:

programming the third group of pixel circuits after programming of the second group of pixel circuits, during a third programming time period during which none of the pixel circuits of the third group of pixels circuits emit light; and

responsive to programming the third group of pixel circuits, emitting light from the third group of pixel circuits.

14. The method of claim 1, wherein the first group of pixel circuits are interlaced with the second group pixel circuits such that the first group of pixel circuits and the second group of pixel circuits are arranged in row interlaced configuration with respect to one another.