Method of making thermally-isolated silicon-based integrated circuits

• US 9,824,932 B1
• Filed: 08/11/2016
• Issued: 11/21/2017
• Est. Priority Date: 08/05/2013
• Status: Active Grant

• Current Assignee: National Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
• Original Assignee: National Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
• Inventors: Wojciechowski, Kenneth, Olsson, Roy, Clews, Peggy J., Bauer, Todd
• Primary Examiner(s): Gondarenko, Natalia
• Application Number:
  US15/234,932
• Time in Patent Office: 467 Days
• Field of Search: 257467, 257401, 257470, 257577, 257622, 257468, 257469, 257415, 257420, 257428, 257429, 438400, 438 50- 55
• CPC Class Codes: B81B 2203/0118 Cantilevers
• CPC Class Codes: B81B 7/0083 Temperature control
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/3213 Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H03H 2009/02181 by application of heat from a heat source
• CPC Class Codes: H03H 3/02 for the manufacture of piezoelectric or electrostrictive resonators or networks H03H3/08 takes precedence

Abstract

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Claims

1. A method of fabricating a thermally isolated integrated circuit and resonator combination, the method comprising the steps of:

a) providing a silicon-based substrate;

b) fabricating at least one integrated circuit comprising a portion of the silicon-based substrate, the at least one integrated circuit comprising an interlevel dielectric layer formed over the silicon-based substrate;

c) forming a silicon release layer on a top surface of the interlevel dielectric layer at a location over the at least one integrated circuit;

d) depositing an isolation layer over a remaining, exposed surface of the interlevel dielectric layer and the silicon release layer;

e) depositing a conductive layer over a structure resulting from step d) and patterning the conductive layer to create a lower electrode;

f) depositing a piezoelectric layer over a structure resulting from step e),

g) depositing a conductive layer over a structure resulting from step f) and patterning the conductive layer to create an upper electrode;

h) patterning a top surface of a structure resulting from step g), wherein the patterning of step h) is performed so as to define (i) a resonator formed by the lower electrode, piezoelectric layer and the upper electrode, (ii) boundaries around at least one region to be thermally isolated and (iii) a support bar region to be further processed to provide a support bar;

i) etching piezoelectric material exposed by the patterning in step h), the etching terminating upon exposure of portions of the silicon release layer, then removing exposed portions of the silicon release layer;

j) etching a structure resulting from step i) to remove exposed regions of the interlevel dielectric layer and a buried oxide insulating layer, exposing the silicon-based substrate; and

k) etching a structure resulting from step j) to remove any remainder of the silicon release layer to isolate the resonator from the silicon-based substrate, the etching also removing a portion of the exposed silicon-based substrate sufficient to release the integrated circuit from the silicon-based substrate, with the support bar maintaining physical contact between the integrated circuit and the silicon-based substrate, creating a suspended structure.

2. The method as in claim 1, wherein in performing step f) a layer of aluminum nitride is deposited.

3. The method as in claim 1, wherein in performing step c) an amorphous silicon layer is deposited.

4. The method as in claim 1, wherein in performing steps e) and g), aluminum contact layers are deposited.

5. The method as in claim 1, wherein in performing step a), a silicon-on-insulator (SOI) substrate is provided.