Semiconductor device

• US 9,825,027 B1
• Filed: 01/22/2017
• Issued: 11/21/2017
• Est. Priority Date: 01/22/2017
• Status: Active Grant

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: Fukunaga, Shunsuke, Kondo, Taro
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Koo, Lamont
• Application Number:
  US15/412,035
• Time in Patent Office: 303 Days
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor device has a plurality of transistors, which have first electrodes in first trenches, and includes: two second trenches, which are formed side by side between the first trenches. A second electrode is formed in each of the two second trenches. A first impurity region is formed between the first trench and the second trench; a second impurity region is formed to abut on the first trench; a third impurity region is formed to abut on the second trench; a fourth impurity region, which is formed between two of the second trenches and has a higher impurity concentration than the first impurity region; and a fifth impurity region is formed below the first impurity region and the fourth impurity region. A third electrode is formed to be electrically connected to the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region.

Claims

1. A semiconductor device having a plurality of transistors, which are arranged in one direction and have first electrodes in first trenches formed in a front surface of a semiconductor substrate, the semiconductor device comprising:

two second trenches, which are formed side by side between the first trenches of two adjacent transistors in the one direction, on the front surface of the semiconductor substrate;

a second electrode, which is formed in each of the two second trenches;

a first impurity region, which has a first conductivity type and is formed between the first trench and the second trench adjacent to the first trench, in the front surface of the semiconductor substrate;

a second impurity region, which has a second conductivity type and is formed to abut on the first trench, in a surface of the first impurity region, the second conductivity type being opposite to the first conductivity type;

a third impurity region, which has the second conductivity type and is formed to abut on the second trench, in the surface of the first impurity region;

a fourth impurity region, which has the first conductivity type and is formed to be in contact with the two second trenches on the front surface of the semiconductor substrate and has a higher impurity concentration than the first impurity region;

a fifth impurity region, which has the second conductivity type and is formed below the first impurity region and the fourth impurity region; and

a third electrode, which is formed on the front surface of the semiconductor substrate and is electrically connected to the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region,

wherein the first impurity region is in contact with both the fifth impurity region and the third electrode, and

wherein the fourth impurity region is in contact with both the fifth impurity region and the third electrode.

2. The semiconductor device according to claim 1, wherein the impurity concentration of the fourth impurity region is more than 10 times as high as the impurity concentration of the first impurity region.

3. The semiconductor device according to claim 1, wherein the fourth impurity region has a smaller plane area than the first impurity region.

4. The semiconductor device according to claim 3, wherein the plane area of the fourth impurity region is from 0.25 times or more to 0.5 times or less as large as the plane area of the first impurity region.

5. The semiconductor device according to claim 1, wherein the impurity concentration of the fourth impurity region has a concentration in a range where an ohmic contact with the third electrode is formed.

6. The semiconductor device according to claim 1, wherein a surface of the fourth impurity region is entirely covered with the third electrode.

7. The semiconductor device according to claim 1, wherein the fourth impurity region has a lower end located further toward the front surface of the semiconductor substrate than a lower end of the second electrode.