Metal layer routing level for vertical FET SRAM and logic cell scaling

• US 9,825,032 B1
• Filed: 11/23/2016
• Issued: 11/21/2017
• Est. Priority Date: 11/23/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Bentley, Steven, Paul, Bipul C.
• Primary Examiner(s): Menz, Douglas
• Application Number:
  US15/360,537
• Time in Patent Office: 363 Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element

Abstract

Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

Claims

1. A device comprising:

first and second pairs of fins formed on a substrate each fin having an active top and an inactive bottom portion, fins of each pair laterally separated in a first direction, and the pairs laterally separated from each other in a second direction perpendicular to the first;

a bottom source/drain (S/D) layer is patterned around the fins on the substrate;

conformal first and second liner layers sequentially formed over the substrate;

a first interlayer dielectric (ILD) formed over the conformal second liner layer;

a metal routing layer formed in the second direction between the pairs of fins on the conformal second liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active top portion;

a first dielectric spacer formed over the first ILD;

a gate all around (GAA) formed on the first dielectric spacer around each fin of the first pair;

a second dielectric spacer formed over the GAA and first dielectric spacer;

a bottom S/D contact cross-couple (xc) or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively; and

a second ILD formed over the substrate.

2. The device according to claim 1, wherein the fins of the first pair form part of a pulldown (PD) and a first pullup (PU) transistor, respectively, and the fins of the second pair form part of a pass gate (PG) and a second PU transistor, respectively.

3. The device according to claim 1, further comprising a liner and oxide layer between the metal routing layer and the first dielectric layer.

4. The device according to claim 1, wherein the GAA is formed with a portion overlapping a portion of the metal routing layer.

5. The device according to claim 1, further comprising top S/D contacts on each fin.

6. A method comprising:

forming first and second pairs of fins on a substrate, each fin having an active channel portion and an inactive bottom portion including part of an access region, fins of each pair laterally separated in a first direction, and the pairs laterally separated in a second direction perpendicular to the first;

patterning a bottom source/drain (S/D) layer around the fins on the substrate;

forming conformal first and second liner layers sequentially over the substrate;

forming a first interlayer dielectric (ILD) over the substrate coplanar with the conformal second liner layer;

forming a trench in the ILD between each pair and between the pairs in the second direction;

forming a metal routing layer along the trench, an upper surface formed below the top active portion;

forming an oxide layer over the metal routing layer, an upper surface below a lower surface of the active top portion;

forming a first dielectric spacer over the substrate;

forming a gate all around (GAA) on the first dielectric spacer around each of the first pair of fins;

forming a second dielectric spacer over the GAA and first dielectric spacer; and

forming a second ILD layer over the substrate.

7. The method according to claim 6, comprising forming the first and second pairs of fins by:

forming a hard mask over the substrate;

etching the hard mask and substrate, revealing the active top portion;

forming a bilayer sidewall spacer on sidewalls of the hard mask and active top portion;

recessing the substrate 40 nanometer (nm) to 100 nm, revealing the inactive bottom portion;

recessing laterally a portion of the inactive bottom portion; and

stripping the bilayer sidewall spacer subsequent to forming the bottom S/D layer in the inactive portion of the fin.

8. The method according to claim 6, comprising forming the bottom S/D layer along sidewalls of the inactive bottom portion.

9. The method according to claim 6, comprising forming the first and second pairs of fins and the bottom S/D layer by:

forming the bottom S/D layer over the substrate;

forming an active fin layer over the bottom S/D layer;

forming a hard mask over the active fin layer;

patterning the hard mask;

etching the active fin layer down to the bottom S/D layer on each side of the patterned hard mask, revealing the active top portion; and

recessing the bottom S/D layer around the active fin layer, revealing the inactive bottom portion.

10. The method according to claim 6, comprising forming the trench by:

etching the first ILD down to the conformal second liner layer between fins of the first pair of fins; and

etching the first ILD and conformal first and second liner layers down to the bottom S/D layer at least between fins of the second pair of fins.

11. The method according to claim 6, further comprising, prior to forming the oxide layer:

recessing the metal routing layer until the upper surface is below the top active portion;

forming a conformal third liner layer on sidewalls of the trench and on the metal routing layer;

filling the trench with an oxide;

recessing the oxide, ILD, and conformal third liner layer down to the upper surface of the inactive bottom portion; and

stripping the conformal first and second liner layers from the active top portion.

12. The method according to claim 6, further comprising:

forming a trench adjacent to the GAA through the second ILD, second dielectric spacer, first dielectric spacer, oxide layer, and conformal third liner layer down to the metal routing layer; and

forming a trench silicide in the trench, the trench silicide connecting the metal routing layer and GAA.

13. The method according to claim 6, comprising forming the GAA partially overlapping the metal routing layer.

14. The method according to claim 13, comprising:

forming a conformal third liner layer on sidewalls of the trench and on the metal routing layer;

filling the trench with an oxide;

recessing the oxide, ILD, and conformal third liner layer down to the upper surface of the inactive bottom portion; and

stripping the conformal oxide and SiN layers from the active top portion, prior to forming the oxide layer; and

forming an opening through the second ILD, second dielectric layer, GAA, first dielectric spacer, oxide layer, and the conformal third liner layer down to the metal routing layer;

filling the opening with a metal layer;

recessing the metal layer down to an upper surface of the GAA;

forming a third dielectric spacer layer on the GAA in the opening of the second dielectric layer; and

forming a second oxide layer in the opening coplanar with the second ILD.