Leakage reduction structures for nanowire transistors

• US 9,825,130 B2
• Filed: 03/14/2013
• Issued: 11/21/2017
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Intel Corporation
• Inventors: Kim, Seiyon, Kuhn, Kelin, Rios, Rafael, Armstrong, Mark
• Primary Examiner(s): Crawford, Latanya N
• Application Number:
  US13/996,845
• Publication Number:
  US 20140264253A1
• Time in Patent Office: 1,713 Days
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors.

Claims

1. A microelectronic structure, comprising:

a microelectronic substrate;

at least one nanowire transistor formed on the microelectronic substrate, wherein the at least one nanowire transistor comprises;

a source structure extending from the microelectronic substrate;

a drain structures extending from the microelectronic substrate; and

at least one nanowire channel extending between the source structure and the drain structure, wherein the at least one nanowire channel is disposed over a microelectronic substrate;

a highly doped underlayer abutting the microelectronic substrate;

a source/drain leakage barrier layer abutting the highly doped underlayer and positioned between the highly doped underlayer and the at least one nanowire channel, wherein the source/drain leakage barrier layer comprises an undoped material layer; and

a gate electrode material surrounding the at least one nanowire channel, wherein a portion of the gate electrode material extends between the at least one nanowire channel and the source/drain leakage barrier layer.

2. The microelectronic structure of claim 1, wherein the highly doped underlayer comprises a dopant layer implanted in the microelectronic substrate.

3. The microelectronic structure of claim 1, wherein the highly doped underlayer comprises a highly doped material layer formed on the microelectronic substrate.

4. The microelectronic structure of claim 3, wherein the highly doped material layer comprises a highly doped epitaxial silicon layer.

5. The microelectronic structure of claim 1, wherein the highly doped underlayer comprises a highly P-doped underlayer and wherein the at least one nanowire transistor comprises at least one NMOS nanowire transistor.

6. The microelectronic structure of claim 1, wherein the highly doped underlayer comprises a highly N-doped underlayer and wherein the at least one nanowire transistor comprises at least one PMOS nanowire transistor.

7. The microelectronic structure of claim 1, wherein a portion of the highly doped underlayer comprises a highly P-doped underlayer portion with the at least one nanowire transistor comprising at least one NMOS nanowire transistor formed thereon, and wherein a portion of the highly doped underlayer comprises a highly N-doped underlayer portion with the at least one nanowire transistor comprising at least one PMOS nanowire transistor formed thereon.

8. The microelectronic structure of claim 1, wherein the source/drain leakage barrier layer has a thickness between about 0.5 and 5.0 nanometers.

9. The microelectronic structure of claim 1, wherein the undoped material layer comprises an epitaxial silicon layer.

10. A method of forming a microelectronic structure, comprising:

forming a microelectronic substrate;

forming at least one nanowire transistor on the microelectronic substrate, comprising;

forming a source structure extending from the microelectronic substrate;

forming a drain structures extending from the microelectronic substrate; and

forming at least one nanowire channel extending between the source structure and the drain structure, wherein the at least one nanowire channel is disposed over a microelectronic substrate;

forming a highly doped underlayer abutting the microelectronic substrate;

forming a source/drain leakage barrier layer abutting the highly doped underlayer and positioned between the highly doped underlayer and the at least one nanowire channel, wherein forming the source/drain leakage barrier layer comprises forming an undoped material layer; and

forming a gate electrode material surrounding the at least one nanowire channel, wherein a portion of the gate electrode material extends between the at least one nanowire channel and the source/drain leakage barrier layer.

11. The method of claim 10, wherein forming the highly doped underlayer comprises implanting a dopant into the microelectronic substrate.

12. The method of claim 10, wherein forming the highly doped underlayer comprises forming a highly doped material layer on the microelectronic substrate.

13. The method of claim 12, wherein forming the highly doped material layer comprises forming a highly doped epitaxial silicon layer.

14. The method of claim 10, wherein forming the highly doped underlayer comprises forming a highly P-doped underlayer and wherein forming the at least one nanowire transistor comprises forming at least one NMOS nanowire transistor.

15. The method of claim 10, wherein forming the highly doped underlayer comprises forming a highly N-doped underlayer and wherein forming the at least one nanowire transistor comprises forming at least one PMOS nanowire transistor.

16. The method of claim 10, wherein forming the highly doped underlayer comprises forming a portion of the highly doped underlayer as a highly P-doped underlayer with the at least one nanowire transistor comprising at least one NMOS nanowire transistor formed thereon, and forming a portion of the highly doped underlayer as a highly N-doped underlayer portion with the at least one nanowire transistor comprising at least one PMOS nanowire transistor formed thereon.

17. The method of claim 10, wherein forming the highly doped underlayer comprises:

forming a first mask over a portion of the microelectronic substrate;

ion implanting one of a P-type or an N-type dopant into an unmasked portion of the microelectronic substrate;

removing the first mask;

forming a second mask over the ion implanted portion of the microelectronic substrate;

ion implanting the other of the P-type or the N-type dopant into an unmasked portion of the microelectronic substrate; and

removing the second mask.

18. The method of claim 10, wherein forming the highly doped underlayer comprises:

forming a first mask over a portion of the microelectronic substrate;

forming a material layer having one of a P-type or an N-type dopant therein on an unmasked portion of the microelectronic substrate;

removing the first mask;

forming a second mask over the ion implanted portion of the microelectronic substrate;

forming a material layer having the other of the P-type or the N-type dopant therein on an unmasked portion of the microelectronic substrate; and

removing the second mask.

19. The method of claim 10, wherein forming the source/drain leakage barrier layer comprising forming the source/drain leakage barrier layer having a thickness between about 0.5 and 5.0 nanometers.

20. The method of claim 10, wherein forming the undoped material layer comprises forming an epitaxial silicon layer.

21. A computing device, comprising:

a board including at least one component;

wherein the at least one component includes at least one microelectronic structure comprising;

a microelectronic substrate;

at least one nanowire transistor formed on the microelectronic substrate, wherein the at least one nanowire transistor comprises;

a source structure extending from the microelectronic substrate;

a drain structures extending from the microelectronic substrate; and

at least one nanowire channel extending between the source structure and the drain structure, wherein the at least one nanowire channel is disposed over a microelectronic substrate;

a highly doped underlayer abutting the microelectronic substrate;

a source/drain leakage barrier layer abutting the highly doped underlayer and positioned between the highly doped underlayer and the at least one nanowire channel, wherein the source/drain leakage barrier layer comprises an undoped material layer; and

a gate electrode material surrounding the at least one nanowire channel, wherein a portion of the gate electrode material extends between the at least one nanowire channel and the source/drain leakage barrier layer.