Semiconductor element and method for producing the same

• US 9,825,137 B2
• Filed: 03/19/2014
• Issued: 11/21/2017
• Est. Priority Date: 09/12/2013
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Kim, Youngjae
• Primary Examiner(s): DINKE, BITEW A
• Application Number:
  US14/219,874
• Publication Number:
  US 20150069536A1
• Time in Patent Office: 1,343 Days
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor element and a method for producing the same are provided. A semiconductor element includes an active region comprising trenches, a termination region outside the active region, a transient region disposed between the active region and the termination region, the transient region including an inside trench, in which a center poly electrode is disposed inside at least one of the trenches of the active region, at least two gate poly electrodes are disposed adjacent to an upper portion of the center poly electrode, a p-body region is disposed between upper portions of the trenches, and a source region is disposed at a side of the gate poly electrodes.

Claims

1. A semiconductor element comprising:

a termination region outside an active region, the active region comprising trenches, wherein a center poly electrode is disposed inside at least one of the trenches;

a transient region disposed between the active region and the termination region, the transient region comprising an inside trench;

at least two gate poly electrodes are disposed adjacent to an upper portion of the center poly electrode;

a p-body region disposed between upper portions of the trenches;

a source region disposed at a side of the gate poly electrodes, wherein the source region is not disposed at the p-body region shared with the gate poly electrode formed in the inside trench;

a channel stopper region disposed in the termination region, the channel stopper region including a via hole; and

an equipotential ring metal disposed over the channel stopper region, the equipotential ring metal electrically connecting to the channel stopper region through the via hole included in the channel stopper region, wherein the via hole penetrates the channel stopper region.

2. The semiconductor element according to claim 1, wherein the active region, the transient region and the termination region are disposed within a substrate, and the termination region does not include a trench.

3. The semiconductor element according to claim 1, further comprising an extension gate poly electrode extending to the termination region from the trench of the transient region.

4. The semiconductor element according to claim 3,

wherein a source metal electrically connects the center poly electrode and the source region, a gate metal electrically connects the extended gate poly electrode, and

the source metal is substantially coplanar to the gate metal.

5. The semiconductor element according to claim 4,

wherein the source metal electrically connects the center poly electrode and the source region through via holes.

6. The semiconductor element according to claim 5,

wherein the source metal comprises aluminum, the via holes comprise tungsten, and a barrier metal comprising titanium or titanium nitride is disposed at a bottom surface of the via holes and the source metal.

7. The semiconductor element according to claim 6,

wherein an insulating film comprising a high temperature low pressure deposition (HLD) oxide film and a borophosphosilicate glass (BPSG) film is disposed between the via holes.

8. The semiconductor element according to claim 4,

wherein the equipotential ring metal is disposed substantially coplanar to the source metal and the gate metal at a periphery of the termination region.

9. The semiconductor element according to claim 8,

wherein the channel stopper region is disposed at a surface of a substrate.

10. The semiconductor element according to claim 9,

wherein the channel stopper region is an n+ region.

11. The semiconductor element according to claim 3,

wherein an oxide layer is disposed under the extension gate poly electrode.

12. The semiconductor element according to claim 11,

wherein the oxide layer extends from at least one of the trenches in the active region to the termination region.

13. The semiconductor element according to claim 1,

wherein the center poly electrode is disposed within the inside trench of the transient region, and the gate poly electrode is disposed within the inside trench of the transient region in a region closer to the active region than to the termination region.

14. The semiconductor element according to claim 5,

wherein a p+ region is disposed at a bottom surface of the via holes.

15. The semiconductor element according to claim 14,

wherein a protective layer is disposed on the source metal, the gate metal and the equipotential ring metal.

16. The semiconductor element according to claim 15,

wherein the protective layer comprises a nitride film.

17. The semiconductor element according to claim 1,

wherein the gate insulating film is disposed between a side of the trench and at least one of the gate poly electrodes, between the gate poly electrodes, and between the center poly electrode and a second center poly electrode, and

wherein the gate insulating film is thicker between the gate poly electrode and the center poly electrode than between the side of the trench and the at least one of the gate poly electrode.

18. The semiconductor element according to claim 1,

wherein a depth of the p-body region is disposed at an intermediate portion of a depth of the gate poly electrode.

19. The semiconductor element according to claim 2,

wherein upper surfaces of the center poly electrode and the gate poly electrodes are substantially coplanar to each other.

20. The semiconductor element according to claim 1,

wherein a depth of the inside trench in the transient region is deeper than a depth of the trenches formed in the active region.

21. The semiconductor element according to claim 1,

wherein a bottom surface of the gate poly electrodes inclines toward the center poly electrode disposed between the gate poly electrodes.

22. The semiconductor element according to claim 1,

wherein a bottom portion of the gate poly electrodes close to the center poly electrode is deeper than a bottom portion of the gate poly electrodes distant from the center poly electrode.

23. The semiconductor element according to claim 1, wherein a p+ region is disposed at a bottom surface of each of the via hole.

24. A semiconductor element comprising:

an active region comprising active trenches, wherein the active trenches comprise a first trench and a second trench, wherein each active trench includes a U-shaped portion of oxide layer, and wherein each U-shaped portion includes a left wall, a bottom, and a right wall;

a termination region outside the active region;

a transient region disposed between the active region and the termination region, the transient region comprising an inside trench;

a first center poly electrode located between a left wall of the first trench and a right wall of the first trench;

a left gate poly electrode located in a top region of the left wall of the first trench;

a right gate poly electrode located in a top region of the right wall of the first trench, wherein the left gate poly electrode and the right gate poly electrode are adjacent to an upper portion of the center poly electrode;

a p-body region located between the right wall of the first trench and a left wall of the second trench, and located horizontally to the right of the right gate poly electrode;

a source region located directly on top of the p-body region;

a channel stopper region disposed in the termination region, the channel stopper region including a via hole that penetrates the channel stopper region; and

an equipotential ring metal disposed over the channel stopper region, the equipotential ring metal electrically connecting to the channel stopper region through the via hole included in the channel stopper region,

wherein the first trench includes an outer left gate insulating film adjacent to a left surface of the left gate poly electrode, and an inner left gate insulating film adjacent to a right surface of the left gate poly electrode,

wherein the outer left gate insulating film has a thin width, the inner left gate insulating film has a thick width, and

wherein the thin width is smaller than the thick width.

25. A semiconductor element comprising:

a termination region disposed adjacent an active region, the active region including a trench;

a transient region disposed between the active region and the termination region, the transient region including an inside trench having a center poly electrode disposed therein, a width of the trench being different from a width of the inside trench;

an extension gate poly electrode disposed above entire planar upper surfaces of the inside trench and the trench;

an equipotential ring electrode disposed in the termination region; and

an insulating layer disposed between the equipotential ring electrode and a metal layer, and between the equipotential ring electrode and a channel stopper region,

wherein via holes respectively electrically connect the metal layer to the equipotential ring electrode and the channel stopper region.

26. A semiconductor element comprising:

a termination region disposed adjacent an active region, the active region including a trench having a center poly electrode disposed therein;

a transient region disposed between the active region and the termination region, the transient region including an inside trench, a width of the trench being different from a width of the inside trench;

an extension gate poly electrode disposed above an entire planar upper surface of the inside trench and a portion of a planar upper surface of the trench;

an equipotential ring electrode and a channel stopper region both disposed in the termination region; and

an insulating layer disposed between the equipotential ring electrode and a metal layer, and between the equipotential ring electrode and a channel stopper region,

wherein via holes respectively electrically connect the metal layer to the equipotential ring electrode and the channel stopper region.