FinFET with dielectric isolated channel

• US 9,825,174 B2
• Filed: 03/25/2016
• Issued: 11/21/2017
• Est. Priority Date: 04/09/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Khakifirooz, Ali, Reznicek, Alexander, Seo, Soon-Cheon
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Stevenson, Andre C
• Application Number:
  US15/080,901
• Publication Number:
  US 20160211377A1
• Time in Patent Office: 606 Days
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Embodiments of the present invention provide a fin type field effect transistor (FinFET) and methods of fabrication. A punchthrough stopper region is formed on a semiconductor substrate. An insulator layer, such as silicon oxide, is formed on the punchthrough stopper. Fins and gates are formed on the insulator layer. The insulator layer is then removed from under the fins, exposing the punchthrough stopper. An epitaxial semiconductor region is grown from the punchthrough stopper to envelop the fins, while the insulator layer remains under the gate. By growing the fin merge epitaxial region mainly from the punchthrough stopper, which is part of the semiconductor substrate, it provides a higher growth rate then when growing from the fins. The higher growth rate provides better epitaxial quality and dopant distribution.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a punchthrough stopper region formed on the semiconductor substrate;

an insulator region formed on a portion of the punchthrough stopper region;

a gate formed on the insulator region;

a fin formed over the punchthrough stopper region, and traversing the gate; and

an epitaxial semiconductor region disposed on the fin, and in direct physical contact with a bottom surface of the fin, and in direct physical contact with the punchthrough stopper region.

2. The semiconductor structure of claim 1, wherein the semiconductor substrate comprises a silicon substrate.

3. The semiconductor structure of claim 1, wherein the punchthrough stopper (PTS) region comprises a doped region of the semiconductor substrate and comprises a (100) crystalline surface.

4. The semiconductor structure of claim 1, wherein the epitaxial semiconductor region is also in direct physical contact with the punchthrough stopper region.

5. The semiconductor structure of claim 2, wherein the punchthrough stopper region comprises arsenic dopants.

6. The semiconductor structure of claim 2, wherein the punchthrough stopper region comprises phosphorous dopants.

7. The semiconductor structure of claim 2, wherein the punchthrough stopper region comprises boron dopants.

8. The semiconductor structure of claim 2, wherein the insulator region comprises silicon oxide.

9. The semiconductor structure of claim 8, wherein the insulator region has a thickness ranging from about 20 nanometers to about 30 nanometers.

10. The semiconductor structure of claim 1, wherein the epitaxial semiconductor region comprises silicon.

11. The semiconductor structure of claim 1, wherein the epitaxial semiconductor region comprises silicon germanium.

12. A semiconductor structure comprising:

a semiconductor substrate;

a punchthrough stopper region formed on the semiconductor substrate;

an insulator region formed on a portion of the punchthrough stopper region;

a gate formed on the insulator region;

a plurality of fins formed over the punchthrough stopper region, and traversing the gate, wherein each fin of the plurality of fins has a width ranging from about 6 nanometers to about 12 nanometers; and

an epitaxial semiconductor region disposed on the plurality of fins, and in direct physical contact with a bottom surface of each fin, and in direct physical contact with the punchthrough stopper region.

13. The semiconductor structure of claim 12, wherein the semiconductor substrate comprises a silicon substrate.

14. The semiconductor structure of claim 12, wherein the punchthrough stopper (PTS) region comprises a doped region of the semiconductor substrate and comprises a (100) crystalline surface.

15. The semiconductor structure of claim 12, wherein the epitaxial semiconductor region is also in direct physical contact with the punchthrough stopper region.

16. The semiconductor structure of claim 13, wherein the punchthrough stopper region comprises arsenic dopants.

17. The semiconductor structure of claim 13, wherein the punchthrough stopper region comprises boron dopants.

18. The semiconductor structure of claim 13, wherein the insulator region comprises silicon oxide.

19. The semiconductor structure of claim 13, wherein the epitaxial semiconductor region comprises silicon.

20. The semiconductor structure of claim 13, wherein the epitaxial semiconductor region comprises silicon germanium.