Read performance of a non-volatile memory device, in particular a non-volatile memory device with buried selection transistor

• US 9,825,186 B2
• Filed: 11/30/2016
• Issued: 11/21/2017
• Est. Priority Date: 03/22/2016
• Status: Active Grant

• Current Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: La Rosa, Francesco, Niel, Stephan, Regnier, Arnaud
• Primary Examiner(s): Hur, J. H.
• Assistant Examiner(s): Ojha, Ajay
• Application Number:
  US15/365,433
• Publication Number:
  US 20170278577A1
• Time in Patent Office: 356 Days
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

The non-volatile memory device comprises memory cells each comprising a selectable state transistor having a floating gate and a control gate. The state transistor is of the depletion-mode type and is advantageously configured so as to have a threshold voltage that is preferably negative when the memory cell is in a virgin state. When the memory cell is read, a read voltage of zero may then be applied to the control gate and also to the control gates of the state transistors of all the memory cells of the memory device.

Claims

1. A non-volatile memory device, comprising:

a first twin pair of memory cells, the first twin pair including first and second memory cells arranged in a first column, the first and second memory cells each including a respective selection transistor and a respective state transistor, the selection transistors of the first twin pair having respective gate terminals coupled to one another;

a second twin pair of memory cells, the second twin pair including third and fourth memory cells arranged in the first column, the third memory cell being adjacent to the second memory cell, the third and fourth memory cells each including a respective selection transistor and a respective state transistor, the selection transistors of the second twin pair having respective gate terminals coupled to one another;

a first bitline coupled to conduction terminals of the state transistors of the first and fourth memory cells; and

a second bitline coupled to conduction terminals of the state transistors of the second and third memory cells, wherein each state transistor having a charge-trapping region and a control gate, the state transistor being configured to store a binary data value and selectively take first and second states respectively corresponding to two logical values of the binary data value, wherein the state transistor is a depletion-mode transistor and is configured, when a control voltage of zero is applied to the said control gate, to be conducting when the state transistor is in the first state and turned off when the state transistor is in the second state.

2. The non-volatile memory device of claim 1, wherein each state transistor is configured so as to be conducting when the state transistor is in a virgin state and when a control voltage of zero is applied to the control gate of the state transistor.

3. The non-volatile memory device according to claim 2, in which each state transistor is configured to have a negative threshold voltage when the state transistor is in a virgin state.

4. The non-volatile memory device according to claim 3, in which the negative threshold voltage is between −

1 volt and −

0.5 volts.

5. The non-volatile memory device according to claim 1, in which each state transistor has a channel implanted at a surface in a substrate.

6. The non-volatile memory device according to claim 5, in which the implanted channel has a depth that is less than or equal to 100 nm.

7. The non-volatile memory device according to claim 5, in which the channel has a dose of implanted dopants between 10¹² atoms/cm² and 10¹⁴ atoms/cm².

8. The non-volatile memory device according to claim 1, further comprising a read circuit configured to apply a read voltage of zero on the control gate of the state transistor of each memory cell during an operation for reading the memory cell.

9. The device according to claim 1, in which each state transistor is a SONOS transistor in which the charge-trapping region includes a layer of silicon nitride between first and second silicon oxide layers.

10. The non-volatile memory device according to claim 1, comprising:

a third twin pair of memory cells, the third twin pair including fifth and sixth memory cells arranged in a second column, the fifth and sixth memory cells each including a respective selection transistor and a respective state transistor, the selection transistors of the third twin pair having respective gate terminals coupled to one another;

a fourth twin pair of memory cells, the fourth twin pair including seventh and eighth memory cells arranged in the second column, the seventh memory cell being adjacent to the sixth memory cell, the seventh and eighth memory cells each including a respective selection transistor and a respective state transistor, the selection transistors of the fourth twin pair having respective gate terminals coupled to one another;

a third bitline coupled to conduction terminals of the state transistors of the fifth and eighth memory cells; and

a fourth bitline coupled to conduction terminals of the state transistors of the sixth and seventh memory cells.

11. The non-volatile memory device according to claim 10, comprising:

a first gate control line coupled to the respective control gates of the state transistors of the first and fifth memory cells;

a second gate control line coupled to the respective control gates of the state transistors of the second and sixth memory cells;

a third gate control line coupled to the respective control gates of the state transistors of the third and seventh memory cells; and

a fourth gate control line coupled to the respective control gates of the state transistors of the fourth and eighth memory cells.

18. The device according to claim 1, in which each state transistor is a SONOS transistor in which the charge-trapping region includes a layer of silicon nitride between first and second silicon oxide layers.

19. The non-volatile memory device according to claim 1, wherein:

the columns include;

a first column that includes first and second twin pairs of memory cells, the first twin pair including first and second memory cells, the second twin pair including third and fourth memory cells, and the third memory cell being adjacent to the second memory cell; and

a second column that includes third and fourth twin pairs of memory cells, the third twin pair including fifth and sixth memory cells, the second twin pair including seventh and eighth memory cells, and the sixth memory cell being adjacent to the seventh memory cell; and

the plurality of bitlines includes a first bitline coupled to conduction terminals of the state transistors of the first and fourth memory cells, a second bitline coupled to conduction terminals of the state transistors of the second and third memory cells, a third bitline coupled to conduction terminals of the state transistors of the fifth and eighth memory cells, and a fourth bitline coupled to conduction terminals of the state transistors of the sixth and seventh memory cells.

20. The non-volatile memory device according to claim 19, wherein the plurality of control gate lines includes:

a first gate control line coupled to the respective control gates of the state transistors of the first and fifth memory cells;

a second gate control line coupled to the respective control gates of the state transistors of the second and sixth memory cells;

a third gate control line coupled to the respective control gates of the state transistors of the third and seventh memory cells; and

a fourth gate control line coupled to the respective control gates of the state transistors of the fourth and eighth memory cells.

12. A method, comprising:

reading a non-volatile memory cell of a memory device that includes a memory plane including rows and columns of memory cells and two bit lines per column, each column of memory cells including pairs of twin memory cells, each pair of twin memory cells having two selection transistors sharing a common gate, two adjacent twin memory cells of the same column not being connected to the same bit line, and two adjacent memory cells of the same column that are not part of the same twin memory cell being connected to the same bit line, each memory cell including a selectable state transistor that is a depletion-mode transistor having a charge trapping region and a control gate, wherein the reading includes applying a read voltage of zero to the control gate of the state transistor of the non-volatile memory cell being read.

13. The method according to claim 12, in which each state transistor is configured so as to have a negative threshold voltage when the state transistor is in a virgin state.

14. The method according to claim 12, comprising applying read voltage of zero to the control gates of the state transistors of all the memory cells of the memory plane.

15. The method according to claim 12, in which the memory cells of at least a part of each row form a page and the method includes reading the memory plane by page.

16. A non-volatile memory device, comprising:

a memory plane including rows and columns of memory cells, each memory cell including a selection transistor, having a control gate, and a selectable state transistor that is a depletion-mode transistor having a charge trapping region and a control gate, each column of memory cells including pairs of twin memory cells, the selection transistors of each pair of twin memory cells sharing a common gate;

a plurality of gate control lines, each control gate line being electrically coupled to the control gates of the state transistors of the memory cells of a respective one of the rows; and

a plurality of bit lines, each column of memory cells being connected to a respective pair of bit lines of the plurality of bit lines, two adjacent twin memory cells of the same column not being connected to the same bit line, and two adjacent memory cells of the same column that are not part of the same twin memory cell being connected to the same bit line.

17. The non-volatile memory device according to claim 16, in which each state transistor is configured to have a negative threshold voltage when the state transistor is in a virgin state.