Semiconductor memory device

• US 9,825,216 B2
• Filed: 08/23/2016
• Issued: 11/21/2017
• Est. Priority Date: 10/16/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Sang Hwan, Kim, Whankyun, Kim, Keewon, Jang, Youngman
• Primary Examiner(s): BERNSTEIN, ALLISON
• Application Number:
  US15/244,498
• Publication Number:
  US 20170110651A1
• Time in Patent Office: 455 Days
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H01F 10/3272 by use of anti-parallel coupled [APC] ferromagnetic layers, e.g. artificial ferrimagnets [AFI], artificial [AAF] or synthetic [SAF] anti-ferromagnets
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

A semiconductor memory device includes free magnetic pattern on a substrate, a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern, and an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern, wherein the first pinned pattern includes first ferromagnetic patterns and anti-ferromagnetic exchange coupling patterns which are alternately stacked.

Claims

1. A semiconductor memory device, comprising:

a free magnetic pattern on a substrate;

a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns;

a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern;

a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern; and

an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern,

wherein the first pinned pattern includes first ferromagnetic patterns and first non-magnetic patterns which are alternately stacked,

wherein the second pinned pattern includes second ferromagnetic patterns and second non-magnetic patterns which are alternately stacked,

wherein the second ferromagnetic patterns include the same ferromagnetic material as the first ferromagnetic patterns, and

wherein the second non-magnetic patterns include a different non-magnetic material from the first non-magnetic patterns.

2. The semiconductor memory device as claimed in claim 1, wherein a number of the first ferromagnetic patterns stacked in the first pinned pattern is smaller than a number of the second ferromagnetic patterns stacked in the second pinned pattern.

3. The semiconductor memory device as claimed in claim 1, wherein:

the first pinned pattern includes an odd number of the first ferromagnetic patterns and an even number of the first non-magnetic patterns, and

a thickness of one even-numbered first ferromagnetic pattern of the first ferromagnetic patterns is greater than a thickness of an odd-numbered first ferromagnetic pattern of the first ferromagnetic patterns.

4. The semiconductor memory device as claimed in claim 1, wherein:

the first pinned pattern includes an even number of the first ferromagnetic patterns and an even number of the first non-magnetic patterns, and

a thickness of an odd-numbered first ferromagnetic pattern of the first ferromagnetic patterns is substantially equal to a thickness of an even-numbered first ferromagnetic pattern of the first ferromagnetic patterns.

5. The semiconductor memory device as claimed in claim 1, wherein thicknesses of the second ferromagnetic patterns of the second pinned pattern are substantially equal to each other.

6. The semiconductor memory device as claimed in claim 1, wherein the free magnetic pattern and the polarization enhancement magnetic pattern are in contact with the tunnel barrier pattern.

7. The semiconductor memory device as claimed in claim 1, wherein the first pinned pattern has a different crystal structure from the polarization enhancement magnetic pattern.

8. The semiconductor memory device as claimed in claim 1, wherein the polarization enhancement magnetic pattern has the same crystal structure as the free magnetic pattern.

9. The semiconductor memory device as claimed in claim 1, wherein the polarization enhancement magnetic pattern includes a magnetic material with a magnetic moment having a magnitude that is greater than a magnitude of a magnetic moment of the first pinned pattern.

10. The semiconductor memory device as claimed in claim 1, wherein each of the first non-magnetic patterns includes a non-magnetic material that couples first ferromagnetic patterns adjacent to each other to have magnetic moments of the adjacent first ferromagnetic patterns anti-parallel to each other.

11. The semiconductor memory device as claimed in claim 1, wherein the intervening pattern includes a non-magnetic material that is in contact with the polarization enhancement magnetic pattern and one of the first ferromagnetic patterns of the first pinned pattern to couple the polarization enhancement magnetic pattern and the one first ferromagnetic pattern in such a way that a magnetic moment of the polarization enhancement magnetic pattern is parallel to a magnetic moment of the one first ferromagnetic pattern.