Dynamic error vector magnitude duty cycle correction

• US 9,825,591 B2
• Filed: 10/13/2016
• Issued: 11/21/2017
• Est. Priority Date: 09/19/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Lam, Lui, Doherty, Mark M.
• Primary Examiner(s): NGUYEN, HIEU P
• Application Number:
  US15/293,073
• Publication Number:
  US 20170033746A1
• Time in Patent Office: 404 Days
• Field of Search: 330136, 330285, 330296, 330289
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/111 the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/165 A filter circuit coupled to the input of an amplifier
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/429 Two or more amplifiers or one amplifier with filters for different frequency bands are coupled in parallel at the input or output
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2203/7209 the gated amplifier being switched from a first band to a second band
• CPC Class Codes: H03F 2203/7221 the gated amplifier being switched on or off by a switch at the output of the amplifier
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H04B 1/04 Circuits

Abstract

Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.

Claims

1. A power amplifier module comprising:

a power amplifier configured to amplify a radio frequency signal;

a low pass filter configured to generate a correction signal based at least partly on an indication of a duty cycle of the power amplifier; and

a bias circuit configured to generate a bias signal based at least partly on the correction signal such that changes in the bias signal are inversely proportional to changes in the duty cycle of the power amplifier, and the bias circuit configured to bias the power amplifier using the bias signal.

2. The power amplifier module of claim 1 wherein the indication of duty cycle of the power amplifier is an enable signal for the power amplifier.

3. The power amplifier module of claim 1 wherein the radio frequency signal is a wireless local area network signal.

4. The power amplifier module of claim 1 wherein the low pass filter includes an integrator configured to integrate the indication of the duty cycle of the power amplifier.

5. The power amplifier module of claim 1 wherein the power amplifier includes a bipolar transistor having a base configured to receive the bias signal.

6. The power amplifier module of claim 1 wherein the bias circuit includes a current source configured to generate a correction current based at least partly on the correction signal.

7. The power amplifier module of claim 1 wherein a single die includes the power amplifier, the low pass filter, and the bias circuit.

8. The power amplifier module of claim 7 wherein the single die is a silicon germanium die.

9. The power amplifier module of claim 1 wherein a first die includes the low pass filter and the bias circuit and a second die includes the power amplifier.

10. An amplifier system comprising:

an amplifier configured to amplify a radio frequency signal;

a duty cycle tracking circuit configured to track a duty cycle of the amplifier and to provide a signal representative of the duty cycle of the amplifier over time, the duty cycle tracking circuit including a low pass filter; and

a bias circuit configured to generate a bias signal based at least partly on the signal representative of the duty cycle of the amplifier over time and to bias the amplifier using the bias signal so as to compensate for variation in amplifier gain due to changes in the duty cycle.

11. The amplifier system of claim 10 wherein the bias circuit includes a current source configured to provide a current that is adjustable based at least partly on the signal representative of the duty cycle of the amplifier over time, and the bias circuit is configured to generate the bias based at least partly on the current.

12. The amplifier system of claim 10 wherein the low pass filter is an integrator.

13. The amplifier system of claim 10 wherein the low pass filter is arranged to receive an enable signal for the amplifier.

14. The amplifier system of claim 10 wherein the radio frequency signal is a wireless local area network signal.

15. The amplifier system of claim 10 wherein the amplifier includes a bipolar transistor having a base configured to receive the bias signal.

16. The amplifier system of claim 10 wherein the amplifier includes a power amplifier.

17. A wireless device comprising:

a power amplifier configured to provide a radio frequency signal;

an antenna configured to transmit the radio frequency signal;

a duty cycle tracking circuit configured to track a duty cycle of the power amplifier and to provide a signal representative of the duty cycle of the power amplifier over time, the duty cycle tracking circuit including a low pass filter; and

a bias circuit configured to generate a bias signal based at least partly on the signal representative of the duty cycle of the power amplifier over time and to bias the power amplifier using the bias signal so as to compensate for variation in power amplifier gain due to changes in the duty cycle of the power amplifier.

18. The wireless device of claim 17 wherein the radio frequency signal is a wireless local area network signal.

19. The wireless device of claim 17 configured as a mobile phone.

20. The wireless device of claim 17 wherein the low pass filter is an integrator configured to receive an enable signal for the power amplifier.