Virtual critical path (VCP) system and associated methods
First Claim
1. A semiconductor chip, comprising:
- a critical path circuit comprising first circuitry defined between an input latch and an output latch, defined to operate in accordance with a system clock signal, wherein;
the first circuitry is configured to perform first logic functions on input data from the input latch to generate output data at the output latch, anda critical path timing characteristic of the critical path circuit is defined as a time delay from clocking out of the input data from the input latch to clocking in of the output data into the output latch; and
a virtual critical path circuit comprising second circuitry defined to operate in accordance with a special clock signal, wherein;
the second circuitry is configured to perform second logic functions on an input value to generate an output value,a virtual critical path timing characteristic of the virtual critical path circuit corresponds to a duration extending from receipt of the input value by the second circuitry to generation of the output value by the second circuitry, the second circuitry configured such that the virtual critical path timing characteristic is substantially equal to the critical path timing characteristic, andthe second logic functions performed on the input value by the second circuitry to generate the output value are different from the first logic functions performed on the input data by the first circuitry to generate the output data;
the virtual critical path circuit further comprising comparison circuitry configured to compare the output value computed by the second circuitry with an expected result value associated with the input value to determine whether a frequency of the special clock signal is acceptable.
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Accused Products
Abstract
A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.
12 Citations
20 Claims
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1. A semiconductor chip, comprising:
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a critical path circuit comprising first circuitry defined between an input latch and an output latch, defined to operate in accordance with a system clock signal, wherein; the first circuitry is configured to perform first logic functions on input data from the input latch to generate output data at the output latch, and a critical path timing characteristic of the critical path circuit is defined as a time delay from clocking out of the input data from the input latch to clocking in of the output data into the output latch; and a virtual critical path circuit comprising second circuitry defined to operate in accordance with a special clock signal, wherein; the second circuitry is configured to perform second logic functions on an input value to generate an output value, a virtual critical path timing characteristic of the virtual critical path circuit corresponds to a duration extending from receipt of the input value by the second circuitry to generation of the output value by the second circuitry, the second circuitry configured such that the virtual critical path timing characteristic is substantially equal to the critical path timing characteristic, and the second logic functions performed on the input value by the second circuitry to generate the output value are different from the first logic functions performed on the input data by the first circuitry to generate the output data; the virtual critical path circuit further comprising comparison circuitry configured to compare the output value computed by the second circuitry with an expected result value associated with the input value to determine whether a frequency of the special clock signal is acceptable. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method comprising:
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operating a virtual critical path circuit defined to operate in accordance with a special clock signal, separate from a system clock signal of a critical path circuit, the critical path circuit comprising first circuitry defined between an input latch and an output latch, the first circuitry configured to perform first logic functions on input data transmitted from the input latch to generate output data at the output latch, the critical path circuit having a critical path timing characteristic defined as a time delay from clocking out of the input data from the input latch to clocking in of the output data into the output latch, the virtual critical path circuit comprising second circuitry configured to perform second logic functions on an input value to generate an output value, wherein; the second logic functions performed by the second circuitry of the virtual critical path circuit on the input value to generate the output value differ from the first logic functions performed by the first circuitry of the critical path circuit, the virtual critical path circuit has a virtual critical path timing characteristic corresponding to a duration extending from receipt of an input value by the second circuitry to generation of a corresponding output value by the second circuitry, the second circuitry configured such that the virtual critical path timing characteristic is substantially equal to the critical path timing characteristic, and wherein operating the virtual critical path circuit further comprises; comparing the output value generated by the second circuitry with an expected result value associated with the input value to determine that a frequency of the special clock signal is acceptable for operation of the critical path circuit; and adjusting a frequency of the system clock signal to match the determined acceptable frequency of the special clock signal. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification