Orthogonal differential vector signaling
First Claim
1. A method comprising:
- receiving a set of N symbols of a codeword on a multi-wire bus, wherein N is an even integer;
generating a set of N−
1 output signals, each output signal of the set of N−
1 output signals generated using a voltage adder circuit to form a respective summation of the N symbols of the codeword, wherein each symbol in the respective summation has a sign applied by the voltage adder circuit determined by a corresponding element in a respective row of a set of N−
1 rows of a non-simple orthogonal matrix, wherein each row of the set of N−
1 rows is (i) mutually orthogonal and (ii) orthogonal to an all-one common mode row; and
generating a set of N−
1 output bits based on the set of N−
1 output signals.
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Abstract
Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.
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Citations
20 Claims
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1. A method comprising:
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receiving a set of N symbols of a codeword on a multi-wire bus, wherein N is an even integer; generating a set of N−
1 output signals, each output signal of the set of N−
1 output signals generated using a voltage adder circuit to form a respective summation of the N symbols of the codeword, wherein each symbol in the respective summation has a sign applied by the voltage adder circuit determined by a corresponding element in a respective row of a set of N−
1 rows of a non-simple orthogonal matrix, wherein each row of the set of N−
1 rows is (i) mutually orthogonal and (ii) orthogonal to an all-one common mode row; andgenerating a set of N−
1 output bits based on the set of N−
1 output signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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a multi-wire bus configured to receive a set of N symbols of a codeword, wherein N is an even integer; a voltage adder circuit configured to generate a set of N−
1 output signals, each output signal of the set of N−
1 output signals generated based on a respective summation of the N symbols of the codeword, wherein each symbol in the respective summation has a sign applied by the voltage adder circuit determined by a corresponding element in a respective row of a set of N−
1 rows of a non-simple orthogonal matrix, wherein each row of the set of N−
1 rows is (i) mutually orthogonal and (ii) orthogonal to an all-one common mode row; anda detector configured to generate a set of N−
1 output bits based on the set of N−
1 output signals. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification