System and method for optimizing link performance with lanes operating at different speeds

• US 9,825,730 B1
• Filed: 09/26/2016
• Issued: 11/21/2017
• Est. Priority Date: 09/26/2016
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Berke, Stuart Allen, Mutnury, Bhyrav M.
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US15/276,329
• Time in Patent Office: 421 Days
• Field of Search: 375219-224, 375257
• CPC Class Codes: H04L 1/0002 by adapting the transmission rate
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER
• CPC Class Codes: H04L 2001/0096 Channel splitting in point-to-point links

Abstract

A serial communication link includes a receiver and a transmitter coupled to the receiver by a first serial communication lane operating at a first speed, and a second serial communication lane operating at a second speed. The second speed is slower than the first speed. The transmitter can include bit steering logic that receives a data stream, provides a first number of bits of the data stream to the first serial communication lane, and provides a second number of bits to the second serial communication lane. The proportion of the first number of bits to the second number of bits is the same as a proportion of the first speed to the second speed.

Claims

1. A serial communication link, comprising:

a receiver; and

a transmitter coupled to the receiver by a first serial communication lane operating at a first speed in a first mode and in a second mode, and by a second serial communication lane operating at the first speed in the first mode and at a second speed in the second mode, the second speed being slower than the first speed.

2. The serial communication link of claim 1, further comprising:

bit steering logic in the transmitter, the bit steering logic including an input to receive a data stream, a first output coupled to the first serial communication lane, and a second output coupled to the second serial communication lane, the bit steering logic configured to output a first number of bits of the data stream on the first output and to output a second number of bits of the data stream on the second output, wherein the first number of bits is equal to the second number of bits in the first mode, and wherein a proportion of the first number of bits to the second number of bits is the same as a proportion of the first speed to the second speed in the second mode.

3. The serial communication link of claim 1, wherein the receiver is configured to determine a first current bit error rate (BER) for the first serial communication lane while operating in the first mode and a second current BER for the second serial communication lane while operating in the first mode.

4. The serial communication link of claim 3, wherein the transmitter is configured to receive the first and second current BERs from the receiver and to determine that the second current BER is higher than a desired BER.

5. The serial communication link of claim 4, wherein the transmitter is configured to switch operation of the serial communication link from the first mode to the second mode in response to determining that the second current BER is higher than a first desired BER.

6. The serial communication link of claim 5, wherein the receiver is configured to determine a third current BER for the second serial communication lane while operating in the second mode, and the transmitter is configured to receive the third current BER from the receiver and to determine that the third current BER is higher than a second desired BER.

7. The serial communication link of claim 6, wherein the transmitter is configured to switch operation of the serial communication link from the second mode to a third mode in response to determining that the third current BER is higher than a second desire BER, wherein in the third mode a third speed of the second communication lane is slower than the second speed and the speed of the of the first serial communication lane is maintained at the first speed.

8. The serial communication link of claim 1, wherein the serial communication link comprises a Peripheral Component Interconnect-Express (PCIe) serial communication link.

9. The serial communication link of claim 1, wherein the serial communication link comprises one of an InfiniBand communication link, a Fibre Channel communication link, and a Cache Coherency Interconnect for Accelerators (CCIX) communication link.

10. A method comprising:

coupling a transmitter of a serial communication link to a receiver of the serial communication link via a first serial communication lane and a second serial communication lane;

operating the first serial communication lane at a first speed in a first mode and in a second mode; and

operating the second serial communication lane at the first speed in the first mode and at a second speed in the second mode, the second speed being slower than the first speed.

11. The method of claim 10, further comprising:

receiving, at bit steering logic in the transmitter, a data stream;

providing, from the bit steering logic, a first number of bits of the data stream to the first serial communication lane; and

providing, from the bit steering logic, a second number of bits of the data stream to the second serial communication lane, wherein the first number of bits is equal to the second number of bits in the first mode, and wherein a proportion of the first number of bits to the second number of bits is the same as a proportion of the first speed to the second speed in the second mode.

12. The method of claim 10, further comprising:

determining, by the receiver, a first current bit error rate (BER) for the first serial communication lane while operating in the first mode and a second current BER for the second serial communication lane while operating in the first mode.

13. The method of claim 12, further comprising:

receiving, by the transmitter, the first and second current BERs from the receiver; and

determining that the second current BER is higher than a desired BER.

14. The method of claim 13, further comprising:

switching, by the transmitter, an operation of the serial communication link from the first mode to the second mode in response to determining that the second current BER is higher than a first desired BER.

15. The method of claim 14, further comprising:

determining, by the receiver, a third current BER for the second serial communication lane while operating in the second mode;

receiving, by the transmitter, the third current BER from the receiver; and

determining, by the transmitter, that the third current BER is higher than a second desired BER.

16. The method of claim 15, further comprising:

switching, by the transmitter, the operation of the serial communication link from the second mode to a third mode in response to determining that the third current BER is higher than a second desire BER, wherein in the third mode, a third speed of the second communication lane is slower than the second speed; and

maintaining, by the transmitter, the speed of the first serial communication link at the first speed in the third mode.

17. A non-transitory computer-readable medium including code for performing a method, the method comprising:

coupling a transmitter of a serial communication link to a receiver of the serial communication link via a first serial communication lane and a second serial communication lane;

operating the first serial communication lane operating at a first speed in a first mode and in a second mode; and

operating the second serial communication lane operating at the first speed in the first mode and at a second speed in the second mode, the second speed being slower than the first speed.

18. The computer-readable medium of claim 17, the method further comprising:

receiving, at bit steering logic in the transmitter, a data stream;

providing, from the bit steering logic, a first number of bits of the data stream to the first serial communication lane; and

providing, from the bit steering logic, a second number of bits of the data stream to the second serial communication lane, wherein the first number of bits is equal to the second number of bits in the first mode and a proportion of the first number of bits to the second number of bits is the same as a proportion of the first speed to the second speed in the second mode.

19. The computer-readable medium of claim 17, the method further comprising:

determining, by the receiver, a first current bit error rate (BER) for the first serial communication lane while operating in the first mode and a second current BER for the second serial communication lane while operating in the first mode;

receiving, by the transmitter, the first and second current BERs from the receiver; and

determining that the second current BER is higher than a desired BER.

20. The computer-readable medium of claim 19, the method further comprising:

switching, by the transmitter, an operation of the serial communication link from the first mode to the second mode in response to determining that the second current BER is higher than a first desired BER.