Load reduced memory module

• US 9,826,638 B2
• Filed: 10/15/2014
• Issued: 11/21/2017
• Est. Priority Date: 10/15/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Rajan, Suresh
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/515,380
• Publication Number:
  US 20150103479A1
• Time in Patent Office: 1,133 Days
• Field of Search: 365 63
• CPC Class Codes: G06F 1/184 Mounting of motherboards
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7803 System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H05K 1/11 Printed elements for providing electric connections to or between printed circuits
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: H05K 2201/10189 Non-printed connector

Abstract

The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

Claims

1. A memory module comprising:

a data buffer component;

a circuit board comprising a plurality of device sites, the plurality of device sites being coupled to the data buffer component, wherein each device site, of the plurality of device sites, is a location on the circuit board at which at least one respective memory device is disposed; and

a command and address (CA) buffer component disposed on the circuit board, wherein the CA buffer component comprises;

a primary interface comprising a first pin to receive a local chip select (CS) signal and a second pin to receive a distant chip select (CS) signal; and

a secondary interface to select a first set of one or more of the plurality of device sites when the local CS signal is received on the first pin or a second set of one or more of the plurality of device sites when the distant CS signal is received on the second pin.

2. The memory module of claim 1, wherein the primary interface comprises a third pin to receive a second distant CS signal.

3. The memory module of claim 1, wherein the CA buffer component further comprises:

a first flip-flop coupled to the first pin;

a second flip-flop coupled to an output of the first flip-flop, wherein an output of the second flip-flop is coupled to the first set of one or more of the plurality of device sites;

an input buffer coupled to the second pin; and

a third flip-flop coupled to an output of the input buffer, wherein an output of the third flip-flop is coupled to the second set of one or more of the plurality of device sites, wherein the first flip-flop, second flip-flop, and third flip-flop are clocked by a timing signal.

4. The memory module of claim 3, wherein the CA buffer component further comprises a phase locked loop (PLL) coupled to a fourth pin to receive a clock signal and to generate the timing signal.

5. The memory module of claim 3, wherein the CA buffer component further comprises an output buffer coupled to the output of the first flip-flop, wherein an output of the output buffer is coupled to the second pin and is to generate a second distant CS signal.

6. The memory module of claim 1, wherein each of the plurality of device sites comprises at least one of a single memory die, a package stack of at least two memory dies, or a die stack of at least two memory dies.

7. The memory module of claim 1, wherein each of the plurality of device sites comprises a double data rate fourth generation (DDR4) dynamic random-access memory (DRAM) device.

8. The memory module of claim 7, wherein the DDR4 DRAM device comprises:

an array;

a data path coupled to the array;

a primary port coupled to the data path;

a secondary port coupled to the data path; and

a command decoder coupled to the array and the data path.

9. The memory module of claim 1, wherein the data buffer component comprises:

a plurality of input ports;

a multiplexer coupled to the plurality of input ports;

control logic coupled to the multiplexer; and

a synchronizer coupled to the control logic and the multiplexer.

10. A method of operating a memory module comprising a command and address (CA) buffer component, a data buffer component, and a circuit board comprising a plurality of device sites, each device site, of the plurality of device sites, being a location on the circuit board at which at least one respective memory device is disposed, the method comprising:

receiving, at a first pin of a primary interface of the CA buffer component of a memory module, a local chip select (CS) signal;

receiving, at a second pin of the primary interface, a distant chip select (CS) signal;

when the local CS signal is received on the first pin, selecting on a secondary interface of the CA buffer component a first set of one or more of a plurality of device sites; and

when the distant CS signal is received on the second pin, selecting a second set of one or more of the plurality of device sites.

11. The method of claim 10, further comprising receiving, at a third pin of the primary interface, a second distant CS signal.

12. The method of claim 10, further comprising:

receiving, at a fourth pin of the primary interface, a clock signal; and

generating, by a phased locked loop (PLL) coupled to the fourth pin, a timing signal based on the clock signal.

13. The method of claim 10, further comprising generating a second distant CS signal using an output buffer of the CA buffer component, the first output buffer being coupled to a first flip-flop that is coupled to the first pin.

14. A memory module comprising:

a circuit board comprising a plurality of device sites, wherein each device site, of the plurality of device sites, is a location on the circuit board at which at least one respective memory device is disposed;

means for buffering data transferred to and from a plurality of device sites;

means for receiving a local chip select (CS) signal;

means for receiving a distant chip select (CS) signal;

means for selecting a first set of one or more of the plurality of device sites when the local CS signal is received; and

means for selecting a second set of one or more of the plurality of device sites when the distant CS signal is received.

15. The memory module of claim 14, further comprising means for receiving a second distant CS signal.

16. The memory module of claim 14, further comprising means for generating a second distant CS signal based on the distant CS signal.

17. The memory module of claim 14, further comprising:

means for receiving a clock signal; and

means for generating a timing signal based on the clock signal.

18. The memory module of claim 14, wherein each of the plurality of device sites comprises at least one of a single memory die, a package stack of at least two memory dies, or a die stack of at least two memory dies.

19. The memory module of claim 14, wherein each of the plurality of device sites comprises a double data rate fourth generation (DDR4) dynamic random-access memory (DRAM) device.

20. The memory module of claim 19, wherein the DDR4 DRAM device comprises:

an array;

a data path coupled to the array;

a primary port coupled to the data path;

a secondary port coupled to the data path; and

a command decoder coupled to the array and the data path.