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Load reduced memory module

  • US 9,826,638 B2
  • Filed: 10/15/2014
  • Issued: 11/21/2017
  • Est. Priority Date: 10/15/2013
  • Status: Active Grant
First Claim
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1. A memory module comprising:

  • a data buffer component;

    a circuit board comprising a plurality of device sites, the plurality of device sites being coupled to the data buffer component, wherein each device site, of the plurality of device sites, is a location on the circuit board at which at least one respective memory device is disposed; and

    a command and address (CA) buffer component disposed on the circuit board, wherein the CA buffer component comprises;

    a primary interface comprising a first pin to receive a local chip select (CS) signal and a second pin to receive a distant chip select (CS) signal; and

    a secondary interface to select a first set of one or more of the plurality of device sites when the local CS signal is received on the first pin or a second set of one or more of the plurality of device sites when the distant CS signal is received on the second pin.

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