Memory system for controlling nonvolatile memory

• US 9,830,079 B2
• Filed: 11/23/2015
• Issued: 11/28/2017
• Est. Priority Date: 07/23/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Kanno, Shinichi
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US14/949,078
• Publication Number:
  US 20170024137A1
• Time in Patent Office: 736 Days
• Field of Search: 714763, 714766
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/06 Digital input from, or digital output to, record carriers , e.g. RAID, emulated record carriers or networked record carriers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.

Claims

1. A memory system comprising:

a nonvolatile memory including a plurality of physical blocks; and

a controller electrically connected to the nonvolatile memory and configured to manage a plurality of namespaces, the plurality of namespaces including at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data, wherein

the controller is configured to;

receive a first request for the first namespace and a second request for the second namespace from a host device, the first request specifying a first number of logical block addresses and a first number of physical blocks, the second request specifying a second number of logical block addresses and a second number of physical blocks;

allocate the first number of physical blocks for the first namespace;

allocate the second number of physical blocks for the second namespace,

allocate a first over-provision area for the first namespace, wherein a remainder which is obtained when a capacity corresponding to the first number of logical block addresses is subtracted from a capacity corresponding to the first number of physical blocks serves as the first over-provision area; and

allocate a second over-provision area for the second namespace, wherein a remainder which is obtained when a capacity corresponding to the second number of logical block addresses is subtracted from a capacity corresponding to the second number of physical blocks serves as the second over-provision area.

2. The memory system of claim 1, wherein a ratio of the capacity of the second over-provision area to the capacity corresponding to the second number of logical block addresses is smaller than a ratio of the capacity of the first over-provision area to the capacity corresponding to the first number of logical block addresses.

3. The memory system of claim 1, wherein the controller is configured to:

write data associated with an ID of the first namespace to the first namespace as the first type of data; and

write data associated with an ID of the second namespace to the second namespace as the second type of data.

4. The memory system of claim 1, wherein the controller is configured to:

receive a first namespace management command requesting creation of the first namespace from the host device, the first namespace management command including a parameter specifying the first number of logical block addresses and a parameter specifying the first number of physical blocks;

create the first namespace;

allocate the first number of physical blocks for the created first namespace;

receive a second namespace management command requesting creation of the second namespace from the host device, the second namespace management command including a parameter specifying the second number of logical block addresses and a parameter specifying the second number of physical blocks;

create the second namespace; and

allocate the second number of physical blocks for the created second namespace.

5. The memory system of claim 4, wherein the controller is configured to:

determine whether allocation of the physical blocks whose number is specified by the parameter in each namespace management command is possible, on the basis of the number of remaining physical blocks of the nonvolatile memory;

notify, when allocation of the specified number of physical blocks is not possible, the host device of an error response.

6. The memory system of claim 1, wherein the controller is configured to:

calculate write amplification of the first namespace by counting an amount of data written to the first namespace by the host device, and an amount of data written to the first namespace by a garbage collection operation of the first namespace;

calculate write amplification of the second namespace by counting an amount of data written to the second namespace by the host device, and an amount of data written to the second namespace by a garbage collection operation of the second namespace; and

provide the write amplification corresponding to each of the first namespace and the second namespace to the host device.

7. The memory system of claim 1, wherein the controller is configured to:

receive a control command requesting starting of garbage collection of a target namespace from the host device;

select target physical blocks, which are to be garbage-collected, from physical blocks for the target namespace; and

execute a garbage collection operation of copying valid data from the target physical blocks to a copy destination free block.

8. The memory system of claim 7, wherein the controller configured to:

manage free blocks created by the garbage collection operation executed for each of the namespaces as shared free blocks of the plurality of namespaces;

select a free block having a least number of program/erase cycles from the shared free blocks; and

allocate the selected free block as the copy destination free block for the target namespace.

9. The memory system of claim 1, wherein

the controller is configured to generate first encoded data by encoding write data by using first coding for reducing wear of a memory cell, to generate second encoded data by adding an error correction code to the first encoded data, and to write the second encoded data to one of the namespaces, and

the controller is further configured to change a ratio between the first encoded data and the error correction code in accordance with the one of the namespaces to which the second encoded data is to be written.

10. The memory system of claim 9, wherein the controller is configured to:

control the ratio between the first encoded data and the error correction code such that second encoded data including first encoded data having a first length and an error correction code having a second length is obtained, when the second encoded data is that which should be written to the first namespace; and

control the ratio between the first encoded data and the error correction code such that second encoded data including first encoded data having a third length less than the first length and an error correction code having a fourth length greater than the second length is obtained, when the second encoded data is that which should be written to the second namespace.

11. The memory system of claim 1, wherein

the controller is configured to execute a striping operation for distributing data across a plurality of storage devices each including the nonvolatile memory, and

each of the plurality of namespaces is arranged to extend over the plurality of storage devices.

12. A memory system comprising:

a nonvolatile memory including a plurality of physical blocks; and

a controller electrically connected to the nonvolatile memory, the controller configured to logically divide the nonvolatile memory into a plurality of areas, the plurality of areas being associated with a plurality of namespaces, the plurality of areas including at least a first area for storing a first type of data, and a second area for storing a second type of data having a lower update frequency than the first type of data, the first area and the second area being associated with a first namespace and a second namespace, wherein

the controller is configured to;

receive a first request for the first namespace and a second request for the second namespace from a host device, the first request specifying a first number of logical block addresses and a first number of physical blocks, the second request specifying a second number of logical block addresses and a second number of physical blocks;

allocate the first number of physical blocks for the first area;

allocate the second number of physical blocks for the second area;

allocate a first over-provision area for the first area, wherein a remainder which is obtained when a capacity corresponding to the first number of logical block addresses is subtracted from a capacity corresponding to the first number of physical blocks serves as the first over-provision area for the first area;

allocate a second over-provision area for the second area, wherein a remainder which is obtained when a capacity corresponding to the second number of logical block addresses is subtracted from a capacity corresponding to the second number of physical blocks serves as the second over-provision area for the second area;

write data associated with an ID of the first namespace to the first area as the first type of data; and

write data associated with an ID of the second namespace to the second area as the second type of data.

13. A memory system comprising:

a nonvolatile memory including a plurality of physical blocks; and

a controller electrically connected to the nonvolatile memory and configured to manage a plurality of namespaces, the plurality of namespaces including at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data, wherein

the controller is configured to;

receive a first request for the first namespace and a second request for the second namespace from a host device, the first request specifying a first number of logical block addresses and a first number of physical blocks, the second request specifying a second number of logical block addresses and a second number of physical blocks;

allocate the first number of physical blocks for the first namespace, the first namespace including a first over-provision area, wherein a remainder which is obtained when a capacity corresponding to the first number of logical block addresses is subtracted from a capacity corresponding to the first number of physical blocks serves as the first over-provision area; and

allocate the second number of physical blocks for the second namespace, the second namespace including a second over-provision area, wherein a remainder which is obtained when a capacity corresponding to the second number of logical block addresses is subtracted from a capacity corresponding to the second number of physical blocks serves as the second over-provision area.

14. The memory system of claim 13, wherein a ratio of the capacity of the second over-provision area to the capacity corresponding to the second number of logical block addresses is smaller than a ratio of the capacity of the first over-provision area to the capacity corresponding to the first number of logical block addresses.