Write redirect

• US 9,830,108 B2
• Filed: 10/12/2015
• Issued: 11/28/2017
• Est. Priority Date: 10/12/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Hsu, Jonathan, Dusija, Gautam Ashok, Kuo, Tienchien, Tuers, Daniel Edward
• Primary Examiner(s): ELMORE, STEPHEN C
• Application Number:
  US14/880,793
• Publication Number:
  US 20170102882A1
• Time in Patent Office: 778 Days
• Field of Search: 711165, 711103, 711154, 711156, 711158, 36518533
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A data storage device includes a memory (including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion), a plurality of data latches, and routing circuitry coupled to the plurality of data latches. The routing circuitry is configured to cause write data, received from a controller, to be stored at a data latch of the plurality of data latches. The routing circuitry is further configured to cause the write data to be copied from the data latch to a particular portion of the memory based on receiving a program mode command after the write data is stored at the data latch, where the program mode command indicates the particular portion as one of the SLC memory portion or the MLC memory portion.

Claims

1. A data storage device comprising:

a memory including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion;

a plurality of data latches; and

routing circuitry coupled to the plurality of data latches and configured to;

cause first write data, received from a controller, to be stored at a first data latch of the plurality of data latches, and

cause the first write data to be copied from the first data latch to a first particular portion of the memory based on a first program mode command received after the first write data is stored at the first data latch, wherein the first program mode command indicates the first particular portion as one of the SLC memory portion or the MLC memory portion.

2. The data storage device of claim 1, wherein the routing circuitry is further configured to cause the first write data to be copied from the first data latch to a second particular portion of the memory based on receiving a commit command after the first write data is stored at the first data latch, wherein the second particular portion corresponds to one of the SLC memory portion or the MLC memory portion.

3. The data storage device of claim 2, wherein the second particular portion is indicated by a second program mode command that is received at the routing circuitry before the first write data is stored at the first data latch.

4. The data storage device of claim 1, wherein the routing circuitry is further configured to receive a second program mode command before the first write data is stored at the first data latch, the second program mode command indicating that the first write data is to be stored at a second particular portion of the memory, wherein the second program mode command indicates the second particular portion as one of the SLC memory portion or the MLC memory portion, and the second particular portion is different than the first particular portion.

5. The data storage device of claim 4, wherein the first particular portion is the SLC memory portion and the second particular portion is the MLC memory portion.

6. The data storage device of claim 1, wherein the routing circuitry is further configured to execute a read command after the first write data is stored at the first data latch and before the first write data is copied from the first data latch to the first particular portion of the memory.

7. The data storage device of claim 1, wherein the routing circuitry includes a processor configured to execute code of a state machine.

8. The data storage device of claim 1, wherein the routing circuitry is further configured to cause the first write data to be stored at the first data latch based on a data latch address that is received before the first write data is received.

9. The data storage device of claim 1, wherein the routing circuitry is further configured to:

cause second write data, received from the controller, to be stored at a second data latch of the plurality of data latches before the first write data is copied from the first data latch to the first particular portion of the memory, and

based on receiving the first program mode command, cause the second write data to be copied from the second data latch to the first particular portion of the memory after the first write data is copied from the first data latch to the first particular portion of the memory.

10. A data storage device comprising:

a memory including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion;

a plurality of data latches coupled to the memory; and

routing circuitry coupled to the plurality of data latches and configured to;

receive a data latch input indicating that first write data is to be stored at a first data latch of the plurality of data latches;

cause the first write data to be stored at the first data latch based on the data latch input;

after causing the first write data to be stored at the first data latch, receive a command that designates the SLC memory portion or the MLC memory portion to store the first write data; and

cause the first write data to be copied from the first data latch to a particular portion of the memory designated by the command.

11. The data storage device of claim 10, wherein the routing circuitry is further configured to execute a read command after the first write data is stored at the first data latch and before the first write data is copied from the first data latch to the particular portion of the memory.

12. The data storage device of claim 10, wherein the routing circuitry includes a processor configured to execute code of a state machine.

13. The data storage device of claim 10, wherein the routing circuitry is further configured to cause the first write data to be stored at the first data latch based on a data latch address that is received before the first write data is received.

14. The data storage device of claim 10, wherein the routing circuitry is further configured to:

cause second write data to be stored at a second data latch of the plurality of data latches before the first write data is copied from the first data latch to the particular portion of the memory; and

based on the command, cause the second write data to be copied from the second data latch to the particular portion of the memory after the first write data is copied from the first data latch to the particular portion of the memory.

15. A method comprising:

at a data storage device including routing circuitry and a memory, the memory including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion, performing;

storing write data at a data latch,

after the write data is stored at the data latch, receiving a first program mode command designating the SLC memory portion or the MLC memory portion to store the write data; and

copied the write data from the data latch to a particular portion of the memory designated by the first program mode command.

16. The method of claim 15, further comprising receiving the write data as part of a command sequence received from a controller coupled to the memory.

17. The method of claim 16, wherein the command sequence comprises a second program mode command that precedes the write data in the command sequence, the second program mode command designating the SLC memory portion or the MLC memory portion to store the write data, and wherein the first program mode command overrides the second program mode command.

18. The method of claim 16, wherein the command sequence comprises a data latch input mode command that precedes the write data in the command sequence, the data latch input mode command indicating that the write data is to be stored at the data latch pending receipt of the first program mode command.

19. The method of claim 15, further comprising:

receiving a read command after the write data is stored at the data latch and before the write data is copied from the data latch to the particular portion of the memory; and

executing the read command before coping the write data from the data latch to the particular portion of the memory.

20. The method of claim 15, further comprising, after the write data is stored at the data latch, receiving address data identifying a particular storage element within the particular portion, wherein the write data is copied to the particular storage element within the particular portion.