Indicating nearing the completion of a transaction

• US 9,830,185 B2
• Filed: 08/21/2015
• Issued: 11/28/2017
• Est. Priority Date: 03/02/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D., Greiner, Dan F., Gschwind, Michael Karl, Michael, Maged M., Shum, Chung-Lung K.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US14/831,966
• Publication Number:
  US 20150355937A1
• Time in Patent Office: 830 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/466 Transaction processing
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

In a multi-processor transaction execution environment, a transaction executes a hint instruction indicating proximity to completion of the transaction. Pending aborts of the transaction due to memory conflicts are suppressed based on the proximity of the transaction to completion.

Claims

1. A method for indicating that a transaction is near to completion in a multi-processor transaction execution environment, the method comprising:

beginning execution, by a processor, of instructions of a transaction in a transaction execution (TX) mode;

executing a transaction hint instruction of the transaction, the hint instruction indicating proximity to transaction completion; and

based on the proximity to transaction completion, determining whether to suppress an abort event from causing an abort of the transaction.

2. The method according to claim 1, further comprising a threshold of completion, wherein the threshold of completion begins at the hint instruction indicating proximity to transaction completion and ends at the last instruction of the transaction.

3. The method according to claim 1, wherein the transaction hint instruction is at least one of:

an instruction generated by a compiler; and

an instruction manually added into assembly code.

4. The method according to claim 1, wherein the transaction hint instruction is a signal to the processor that the transaction is near to completion;

and

based on the transaction being near to completion, delaying by the processor an event that causes the abort of the transaction.

5. The method according to claim 1, wherein the transaction hint instruction precedes in program order any one of:

a final computation in the transaction; and

a final memory access in the transaction.

6. The method according to claim 1, wherein based on the computer processor receiving the transaction hint instruction and being unable to delay the abort of the transaction, the transaction aborts.