Fast saving of data during power interruption in data storage systems

• US 9,830,257 B1
• Filed: 08/14/2013
• Issued: 11/28/2017
• Est. Priority Date: 06/12/2013
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Booth, Jing, Silva, Stephen J., Ha, Justin
• Primary Examiner(s): Rossiter, Sean D
• Assistant Examiner(s): Choi, Charles
• Application Number:
  US13/967,292
• Time in Patent Office: 1,567 Days
• Field of Search: None
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/313 In storage device
• CPC Class Codes: G06F 2212/461 Sector or disk block
• CPC Class Codes: G06F 2212/466 Metadata, control data
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of systems and methods that ensure integrity of data during unexpected power interruption of loss are disclosed. In some embodiments, critical data is saved quickly and efficiently using backup power. Data integrity is ensured even when the reliability of backup power sources is an issue. In some embodiments, by skipping the updating and saving of system data while operating on backup power, significant reduction of time for saving critical data can be achieved. System data can be restored next time the data storage system is restarted. Improvements of data storage system reliability are thereby attained.

Claims

1. A non-volatile data storage system, comprising:

a non-volatile memory array comprising a plurality of memory die;

a volatile memory; and

a controller configured to;

maintain a mapping associating a set of physical addresses in the non-volatile memory array where host system data is stored with a set of logical addresses, wherein at least a portion of the mapping is stored in the volatile memory during operation,

detect, on an indication of a power shutdown, whether the power shutdown is an unexpected interruption of power or an expected interruption of power,

in response to detecting the unexpected interruption of power, write host system data stored in the volatile memory along with one or more mapping data headers to one or more first memory locations in one or more super blocks of the non-volatile memory array, each superblock comprising a plurality of memory blocks in multiple memory die of the plurality of memory die, the one or more mapping data headers comprising physical addresses of second memory locations within the non-volatile memory array that are designated for storing the host system data written to the one or more first memory locations in response to detecting the unexpected interruption of power, the first memory locations being different than the second memory locations, the host system data and one or more mapping data headers being written without updating the mapping or storing mapping updates in the non-volatile memory array, and

upon resuming operation following the unexpected interruption of power, scan the one or more superblocks for the one or more mapping data headers comprising the physical addresses of the second memory locations.

2. The non-volatile data storage system of claim 1, wherein the one or more mapping data headers comprises one or more logical addresses associated with host system data stored in the volatile memory and written to the non-volatile memory array.

3. The non-volatile data storage system of claim 2, wherein, upon resuming operation following the unexpected interruption of power, the controller is further configured to update the mapping using the one or more mapping data headers.

4. The non-volatile data storage system of claim 1, wherein the controller is further configured to:

in response to detecting the unexpected interruption of power, store in a boot memory region of the non-volatile memory array identification information corresponding to one or more non-volatile memory array regions where host system data stored in the volatile memory is written.

5. The non-volatile data storage system of claim 4, wherein, upon resuming operation following the unexpected interruption of power, the controller is further configured to update the mapping using the one or more mapping data headers metadata.

6. The non-volatile data storage system of claim 5, further comprising a hardware module configured to scan the one or more non-volatile memory array regions where host system data stored in the volatile memory was written for the one or more mapping data headers.

7. The non-volatile data storage system of claim 1, further comprising a primary power source configured to provide power during operation and a backup power source configured to provide power during the unexpected interruption of power provided by the primary power source.

8. The non-volatile data storage system of claim 7, wherein the backup power source comprises one or more of capacitors or other power storage devices.

9. The non-volatile data storage system of claim 1, wherein the controller is further configured to:

in response to detecting the expected interruption of power, perform shutdown operations comprising writing host system data stored in the volatile memory to the non-volatile memory array, updating the mapping, and storing mapping updates in the non-volatile memory array.

10. The non-volatile data storage system of claim 1, wherein the controller is further configured to power off the volatile memory after host system data stored in the volatile memory has been stored in the non-volatile memory array.

11. In a non-volatile data storage system comprising a controller, a volatile memory, and a non-volatile memory array comprising a plurality of memory die, a method of storing data, the method comprising:

maintaining a mapping associating a set of physical addresses in the non-volatile memory array where host system data is stored with a set of logical addresses, wherein at least a portion of the mapping is stored in the volatile memory during operation;

detect, on an indication of a power shutdown, whether the power shutdown is an unexpected interruption of power or an expected interruption of power;

in response to detecting an unexpected interruption of power, writing host system data stored in the volatile memory along with one or more mapping data headers to one or more first memory locations in one or more super blocks of the non-volatile memory array, each superblock comprising a plurality of memory blocks in multiple memory die of the plurality of memory die, the one or more mapping data headers comprising physical addresses of second memory locations within the non-volatile memory array that are designated for storing the host system data written to the one or more first memory locations in response to detecting the unexpected interruption of power, the first memory locations being different than the second memory locations, the host system data and one or more mapping data headers being written without updating the mapping or storing mapping updates in the non-volatile memory array; and

upon resuming operation following the unexpected interruption of power, scanning the one or more superblocks for the one or more mapping data headers comprising the physical addresses of the second memory locations,

wherein the method is performed under control of the controller.

12. The method of claim 11, wherein the one or more mapping data headers comprises one or more logical addresses associated with host system data stored in the volatile memory and written to the non-volatile memory array.

13. The method of claim 12, further comprising updating the mapping using the one or more mapping data headers upon resuming operation following the unexpected interruption of power.

14. The method of claim 11, further comprising:

in response to detecting the unexpected interruption of power, storing in a boot memory region of the non-volatile memory array identification information corresponding to one or more non-volatile memory array regions where host system data stored in the volatile memory is written.

15. The method of claim 14, further comprising:

upon resuming operation following the unexpected interruption of power updating the mapping using the one or more mapping data headers.

16. The method of claim 11, further comprising providing power during operation from a primary power source and providing power during the unexpected interruption of power provided by the primary power source from a backup power source.

17. The method of claim 16, wherein the backup power source comprises one or more of capacitors or other power storage devices.

18. The method of claim 11, further comprising:

in response to detecting the expected interruption of power, performing shutdown operations comprising writing host system data stored in the volatile memory to the non-volatile memory array, updating the mapping, and storing mapping updates in the non-volatile memory array.

19. The method of claim 11, further comprising powering off the volatile memory after host system data stored in the volatile memory has been stored in the non-volatile memory array.