Semiconductor device and electronic appliance

• US 9,830,878 B2
• Filed: 06/07/2016
• Issued: 11/28/2017
• Est. Priority Date: 09/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Umezaki, Atsushi
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US15/175,189
• Publication Number:
  US 20160293129A1
• Time in Patent Office: 539 Days
• Field of Search: None
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/018557 Coupling arrangements; Impedance matching circuits
• CPC Class Codes: H03K 19/018571 of complementary type, e.g. CMOS

Abstract

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a sixth transistor,

wherein;

a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor;

one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor;

one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor;

one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor;

a gate of the first transistor is directly connected to the one of the source and the drain of the third transistor;

a gate of the second transistor is directly connected to a gate of the fourth transistor;

the gate of the second transistor is directly connected to the one of the source and the drain of the fifth transistor;

a gate of the third transistor is directly connected to a gate of the sixth transistor;

a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the fourth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the sixth transistor;

a clock signal is inputted to the other of the source and the drain of the fifth transistor;

a first signal is inputted to the gate of the third transistor; and

a second signal is outputted from the one of the source and the drain of the first transistor.

5. A display device comprising the semiconductor device according to claim 1, comprising:

a scan line driver circuit over a substrate; and

a pixel portion over the substrate,

wherein;

the scan line driver circuit comprises;

the first transistor;

the second transistor;

the third transistor;

the fourth transistor;

the fifth transistor; and

the sixth transistor.

17. An electronic appliance including the semiconductor device according to claim 1.

2. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor;

an eighth transistor;

a ninth transistor;

a tenth transistor;

an eleventh transistor; and

a twelfth transistor,

wherein;

a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor includes an oxide semiconductor;

one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor;

one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor;

one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor;

a gate of the first transistor is directly connected to the one of the source and the drain of the third transistor;

a gate of the second transistor is directly connected to a gate of the fourth transistor;

the gate of the second transistor is directly connected to the one of the source and the drain of the fifth transistor;

a gate of the third transistor is directly connected to a gate of the sixth transistor;

a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor;

one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor;

one of a source and a drain of the ninth transistor is directly connected to one of a source and a drain of the tenth transistor;

one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor;

a gate of the seventh transistor is directly connected to the one of the source and the drain of the ninth transistor;

a gate of the eighth transistor is directly connected to a gate of the tenth transistor;

the gate of the eighth transistor is directly connected to the one of the source and the drain of the eleventh transistor;

a gate of the ninth transistor is directly connected to a gate of the twelfth transistor;

a gate of the eleventh transistor is directly connected to the other of the source and the drain of the eleventh transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the fourth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the sixth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the eighth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the tenth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the twelfth transistor;

a first clock signal is inputted to the other of the source and the drain of the fifth transistor;

a second clock signal is inputted to the other of the source and the drain of the eleventh transistor;

a first signal is inputted to the gate of the third transistor;

a second signal is outputted from the one of the source and the drain of the first transistor;

a third signal is inputted to the gate of the ninth transistor; and

a fourth signal is outputted from the one of the source and the drain of the seventh transistor.

6. A display device comprising the semiconductor device according to claim 2, comprising:

a scan line driver circuit over a substrate; and

a pixel portion over the substrate,

wherein;

the scan line driver circuit comprises;

the first transistor;

the second transistor;

the third transistor;

the fourth transistor;

the fifth transistor;

the sixth transistor;

the seventh transistor;

the eighth transistor;

the ninth transistor;

the tenth transistor;

the eleventh transistor; and

the twelfth transistor.

18. An electronic appliance including the semiconductor device according to claim 2.

3. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a sixth transistor,

wherein;

a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor;

a channel width of the first transistor is larger than a channel width of the second transistor,

the channel width of the first transistor is larger than a channel width of the third transistor,

the channel width of the first transistor is larger than a channel width of the fourth transistor,

the channel width of the first transistor is larger than a channel width of the fifth transistor,

the channel width of the first transistor is larger than a channel width of the sixth transistor,

the channel width of the second transistor is larger than the channel width of the third transistor,

the channel width of the second transistor is larger than the channel width of the fifth transistor,

the channel width of the second transistor is larger than the channel width of the sixth transistor,

one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor;

one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor;

one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor;

a gate of the first transistor is directly connected to the one of the source and the drain of the third transistor;

a gate of the second transistor is directly connected to a gate of the fourth transistor;

the gate of the second transistor is directly connected to the one of the source and the drain of the fifth transistor;

a gate of the third transistor is directly connected to a gate of the sixth transistor;

a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the fourth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the sixth transistor;

a clock signal is inputted to the other of the source and the drain of the fifth transistor;

a first signal is inputted to the gate of the third transistor; and

a second signal is outputted from the one of the source and the drain of the first transistor.

7. A display device comprising the semiconductor device according to claim 3, comprising:

a scan line driver circuit over a substrate; and

a pixel portion over the substrate,

wherein;

the scan line driver circuit comprises;

the first transistor;

the second transistor;

the third transistor;

the fourth transistor;

the fifth transistor; and

the sixth transistor.

19. An electronic appliance including the semiconductor device according to claim 3.

4. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor;

an eighth transistor;

a ninth transistor;

a tenth transistor;

an eleventh transistor; and

a twelfth transistor,

wherein;

a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor includes an oxide semiconductor;

a channel width of the first transistor is larger than a channel width of the second transistor,

the channel width of the first transistor is larger than a channel width of the third transistor,

the channel width of the first transistor is larger than a channel width of the fourth transistor,

the channel width of the first transistor is larger than a channel width of the fifth transistor,

the channel width of the first transistor is larger than a channel width of the sixth transistor,

the channel width of the second transistor is larger than the channel width of the third transistor,

the channel width of the second transistor is larger than the channel width of the fifth transistor,

the channel width of the second transistor is larger than the channel width of the sixth transistor,

a channel width of the seventh transistor is larger than a channel width of the eighth transistor,

the channel width of the seventh transistor is larger than a channel width of the ninth transistor,

the channel width of the seventh transistor is larger than a channel width of the tenth transistor,

the channel width of the seventh transistor is larger than a channel width of the eleventh transistor,

the channel width of the seventh transistor is larger than a channel width of the twelfth transistor,

the channel width of the eighth transistor is larger than the channel width of the ninth transistor,

the channel width of the eighth transistor is larger than the channel width of the eleventh transistor,

the channel width of the eighth transistor is larger than the channel width of the twelfth transistor,

one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor;

one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor;

one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor;

a gate of the first transistor is directly connected to the one of the source and the drain of the third transistor;

a gate of the second transistor is directly connected to a gate of the fourth transistor;

the gate of the second transistor is directly connected to the one of the source and the drain of the fifth transistor;

a gate of the third transistor is directly connected to a gate of the sixth transistor;

a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor;

one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor;

one of a source and a drain of the ninth transistor is directly connected to one of a source and a drain of the tenth transistor;

one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor;

a gate of the seventh transistor is directly connected to the one of the source and the drain of the ninth transistor;

a gate of the eighth transistor is directly connected to a gate of the tenth transistor;

the gate of the eighth transistor is directly connected to the one of the source and the drain of the eleventh transistor;

a gate of the ninth transistor is directly connected to a gate of the twelfth transistor;

a gate of the eleventh transistor is directly connected to the other of the source and the drain of the eleventh transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the fourth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the sixth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the eighth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the tenth transistor;

the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the twelfth transistor;

a first clock signal is inputted to the other of the source and the drain of the fifth transistor;

a second clock signal is inputted to the other of the source and the drain of the eleventh transistor;

a first signal is inputted to the gate of the third transistor;

a second signal is outputted from the one of the source and the drain of the first transistor;

a third signal is inputted to the gate of the ninth transistor; and

a fourth signal is outputted from the one of the source and the drain of the seventh transistor.

8. A display device comprising the semiconductor device according to claim 4, comprising:

a scan line driver circuit over a substrate; and

a pixel portion over the substrate,

wherein;

the scan line driver circuit comprises;

the first transistor;

the second transistor;

the third transistor;

the fourth transistor;

the fifth transistor;

the sixth transistor;

the seventh transistor;

the eighth transistor;

the ninth transistor;

the tenth transistor;

the eleventh transistor; and

the twelfth transistor.

20. An electronic appliance including the semiconductor device according to claim 4.

9. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a sixth transistor,

wherein;

a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor;

one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;

one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;

one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor;

a gate of the first transistor is electrically connected to the one of the source and the drain of the third transistor;

a gate of the second transistor is electrically connected to a gate of the fourth transistor;

the gate of the second transistor is electrically connected to the one of the source and the drain of the fifth transistor;

a gate of the third transistor is electrically connected to a gate of the sixth transistor;

a gate of the fifth transistor is electrically connected to the other of the source and the drain of the fifth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the sixth transistor;

a clock signal is inputted to the other of the source and the drain of the fifth transistor;

a first signal is inputted to the gate of the third transistor; and

a second signal is outputted from the one of the source and the drain of the first transistor.

13. A display device comprising the semiconductor device according to claim 9, comprising:

a scan line driver circuit over a substrate; and

a pixel portion over the substrate,

wherein;

the scan line driver circuit comprises;

the first transistor;

the second transistor;

the third transistor;

the fourth transistor;

the fifth transistor; and

the sixth transistor.

21. An electronic appliance including the semiconductor device according to claim 9.

10. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor;

an eighth transistor;

a ninth transistor;

a tenth transistor;

an eleventh transistor; and

a twelfth transistor,

wherein;

a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor includes an oxide semiconductor;

one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;

one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;

one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor;

a gate of the first transistor is electrically connected to the one of the source and the drain of the third transistor;

a gate of the second transistor is electrically connected to a gate of the fourth transistor;

the gate of the second transistor is electrically connected to the one of the source and the drain of the fifth transistor;

a gate of the third transistor is electrically connected to a gate of the sixth transistor;

a gate of the fifth transistor is electrically connected to the other of the source and the drain of the fifth transistor;

one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor;

one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor;

one of a source and a drain of the eleventh transistor is electrically connected to one of a source and a drain of the twelfth transistor;

a gate of the seventh transistor is electrically connected to the one of the source and the drain of the ninth transistor;

a gate of the eighth transistor is electrically connected to a gate of the tenth transistor;

the gate of the eighth transistor is electrically connected to the one of the source and the drain of the eleventh transistor;

a gate of the ninth transistor is electrically connected to a gate of the twelfth transistor;

a gate of the eleventh transistor is electrically connected to the other of the source and the drain of the eleventh transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the sixth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the eighth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the tenth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the twelfth transistor;

a first clock signal is inputted to the other of the source and the drain of the fifth transistor;

a second clock signal is inputted to the other of the source and the drain of the eleventh transistor;

a first signal is inputted to the gate of the third transistor;

a second signal is outputted from the one of the source and the drain of the first transistor;

a third signal is inputted to the gate of the ninth transistor; and

a fourth signal is outputted from the one of the source and the drain of the seventh transistor.

14. A display device comprising the semiconductor device according to claim 10, comprising:

a scan line driver circuit over a substrate; and

a pixel portion over the substrate,

wherein;

the scan line driver circuit comprises;

the first transistor;

the second transistor;

the third transistor;

the fourth transistor;

the fifth transistor;

the sixth transistor;

the seventh transistor;

the eighth transistor;

the ninth transistor;

the tenth transistor;

the eleventh transistor; and

the twelfth transistor.

22. An electronic appliance including the semiconductor device according to claim 10.

11. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a sixth transistor,

wherein;

a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor;

a channel width of the first transistor is larger than a channel width of the second transistor,

the channel width of the first transistor is larger than a channel width of the third transistor,

the channel width of the first transistor is larger than a channel width of the fourth transistor,

the channel width of the first transistor is larger than a channel width of the fifth transistor,

the channel width of the first transistor is larger than a channel width of the sixth transistor,

the channel width of the second transistor is larger than the channel width of the third transistor,

the channel width of the second transistor is larger than the channel width of the fifth transistor,

the channel width of the second transistor is larger than the channel width of the sixth transistor,

one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;

one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;

one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor;

a gate of the first transistor is electrically connected to the one of the source and the drain of the third transistor;

a gate of the second transistor is electrically connected to a gate of the fourth transistor;

the gate of the second transistor is electrically connected to the one of the source and the drain of the fifth transistor;

a gate of the third transistor is electrically connected to a gate of the sixth transistor;

a gate of the fifth transistor is electrically connected to the other of the source and the drain of the fifth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the sixth transistor;

a clock signal is inputted to the other of the source and the drain of the fifth transistor;

a first signal is inputted to the gate of the third transistor; and

a second signal is outputted from the one of the source and the drain of the first transistor.

15. A display device comprising the semiconductor device according to claim 11, comprising:

a scan line driver circuit over a substrate; and

a pixel portion over the substrate,

wherein;

the scan line driver circuit comprises;

the first transistor;

the second transistor;

the third transistor;

the fourth transistor;

the fifth transistor; and

the sixth transistor.

23. An electronic appliance including the semiconductor device according to claim 11.

12. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor;

an eighth transistor;

a ninth transistor;

a tenth transistor;

an eleventh transistor; and

a twelfth transistor,

wherein;

a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor includes an oxide semiconductor;

a channel width of the first transistor is larger than a channel width of the second transistor,

the channel width of the first transistor is larger than a channel width of the third transistor,

the channel width of the first transistor is larger than a channel width of the fourth transistor,

the channel width of the first transistor is larger than a channel width of the fifth transistor,

the channel width of the first transistor is larger than a channel width of the sixth transistor,

the channel width of the second transistor is larger than the channel width of the third transistor,

the channel width of the second transistor is larger than the channel width of the fifth transistor,

the channel width of the second transistor is larger than the channel width of the sixth transistor,

a channel width of the seventh transistor is larger than a channel width of the eighth transistor,

the channel width of the seventh transistor is larger than a channel width of the ninth transistor,

the channel width of the seventh transistor is larger than a channel width of the tenth transistor,

the channel width of the seventh transistor is larger than a channel width of the eleventh transistor,

the channel width of the seventh transistor is larger than a channel width of the twelfth transistor,

the channel width of the eighth transistor is larger than the channel width of the ninth transistor,

the channel width of the eighth transistor is larger than the channel width of the eleventh transistor,

the channel width of the eighth transistor is larger than the channel width of the twelfth transistor,

one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;

one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;

one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor;

a gate of the first transistor is electrically connected to the one of the source and the drain of the third transistor;

a gate of the second transistor is electrically connected to a gate of the fourth transistor;

the gate of the second transistor is electrically connected to the one of the source and the drain of the fifth transistor;

a gate of the third transistor is electrically connected to a gate of the sixth transistor;

a gate of the fifth transistor is electrically connected to the other of the source and the drain of the fifth transistor;

one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor;

one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor;

one of a source and a drain of the eleventh transistor is electrically connected to one of a source and a drain of the twelfth transistor;

a gate of the seventh transistor is electrically connected to the one of the source and the drain of the ninth transistor;

a gate of the eighth transistor is electrically connected to a gate of the tenth transistor;

the gate of the eighth transistor is electrically connected to the one of the source and the drain of the eleventh transistor;

a gate of the ninth transistor is electrically connected to a gate of the twelfth transistor;

a gate of the eleventh transistor is electrically connected to the other of the source and the drain of the eleventh transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the sixth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the eighth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the tenth transistor;

the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the twelfth transistor;

a first clock signal is inputted to the other of the source and the drain of the fifth transistor;

a second clock signal is inputted to the other of the source and the drain of the eleventh transistor;

a first signal is inputted to the gate of the third transistor;

a second signal is outputted from the one of the source and the drain of the first transistor;

a third signal is inputted to the gate of the ninth transistor; and

a fourth signal is outputted from the one of the source and the drain of the seventh transistor.

16. A display device comprising the semiconductor device according to claim 12, comprising:

a scan line driver circuit over a substrate; and

a pixel portion over the substrate,

wherein;

the scan line driver circuit comprises;

the first transistor;

the second transistor;

the third transistor;

the fourth transistor;

the fifth transistor;

the sixth transistor;

the seventh transistor;

the eighth transistor;

the ninth transistor;

the tenth transistor;

the eleventh transistor; and

the twelfth transistor.

24. An electronic appliance including the semiconductor device according to claim 12.