Method and system for dynamic power management of memories

• US 9,830,954 B2
• Filed: 03/23/2011
• Issued: 11/28/2017
• Est. Priority Date: 03/23/2011
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hacking, Lance E., Park, Hee-Jun
• Primary Examiner(s): King, Douglas
• Application Number:
  US13/069,647
• Publication Number:
  US 20120243364A1
• Time in Patent Office: 2,442 Days
• Field of Search: 365227, 365226, 365222, 36523315
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for dynamic power management of memories. In one embodiment of the invention, the power consumption of the memories is reduced based on the operating state of the memories. For example, in one embodiment of the invention, the power supply to the memories is reduced when the memories are in an inactive state by reducing and/or turning off the input voltage(s) to the memories. In one embodiment of the invention, the processing unit dynamically changes the strength of the On-Die Termination pull-up/pull-down resistance based on the memory operating mode, memory voltage, and memory temperature.

Claims

1. A method comprising:

determining that a memory device is in an inactive state; and

in response to determining that the memory device is in the inactive state, determining whether a power consumption of the memory device may be reduced based, at least in part, on a temperature of the memory device, including;

in response to determining the temperature of the memory device is below a temperature threshold, communicating with a voltage regulator coupled with the memory device to reduce a supply voltage output to the memory device, wherein the reduced supply voltage is set between a first voltage level and a second voltage level, the second voltage level being higher than the first voltage level, wherein the memory device fails if the supply voltage is set below the first voltage level when the temperature of the memory device is below the temperature threshold, and wherein the second voltage level is a memory device manufacturer specified minimum level of the supply voltage required to operate the memory device correctly for all memory states; and

in response to determining the temperature of the memory device is above the temperature threshold, maintaining the supply voltage output to the memory device.

2. The method of claim 1, wherein the inactive state comprises a self refresh mode of the memory device.

3. The method of claim 1, further comprising:

communicating with the voltage regulator coupled with the memory device to disable a termination voltage of the memory device.

4. The method of claim 1, further comprising:

changing an on-die termination of one or more signals of a processor that are coupled with the memory device.

5. An apparatus comprising:

processor logic circuitry and/or stored program code to;

determine that a memory device is in an inactive state; and

in response to determining that the memory device is in the inactive state, determine whether a power consumption of the memory device may be reduced based, at least in part, on a temperature of the memory device, including;

in response to determining the temperature of the memory device is below a temperature threshold, communicate with a voltage regulator coupled with the memory device to reduce a supply voltage output to the memory device, wherein the reduced supply voltage is set between a first voltage level and a second voltage level, the second voltage level being higher than the first voltage level, wherein the memory device fails if the supply voltage is set below the first voltage level when the temperature of the memory device is below the temperature threshold, and wherein the second voltage level is a memory device manufacturer specified minimum level of the supply voltage required to operate the memory device correctly for all memory states; and

in response to determining the temperature of the memory device is above the temperature threshold, maintain the supply voltage of the memory device.

6. The apparatus of claim 5, wherein the processor logic circuitry and/or program code is further to dynamically change a strength of on-die termination of one or more signals coupled with the memory device based at least in part on an operating mode of the memory device, on supply voltage of the memory device, or on the temperature of the memory device.

7. The apparatus of claim 6, wherein the processor logic circuitry and/or program code is to dynamically change the strength of on-die termination of the one or more signals coupled with the memory device based at least in part on the operating mode of the memory device is to:

dynamically change a strength of pull down resistors of at least one of the one or more signals coupled with the memory device; and

dynamically change a strength of pull up resistors of at least one of the one or more signals coupled with the memory device.

8. The apparatus of claim 5, wherein the processor logic circuitry and/or program code is further to:

communicate with the voltage regulator coupled with the memory device to disable a termination voltage of the memory device.

9. The apparatus of claim 5, wherein the inactive state comprises a self-refresh state.

10. A system comprising:

a memory device;

a voltage regulator coupled with the memory device; and

processor logic circuitry and/or program code to;

determine that the memory device is in an inactive state; and

in response to determining that the memory device is in the inactive state, determine whether a power consumption of the memory device may be reduced based, at least in part, on a temperature of the memory device, including;

in response to determining the temperature of the memory device is below a temperature threshold, communicate with the voltage regulator to reduce a supply voltage of the memory device, wherein the reduced supply voltage is set between a first voltage level and a second voltage level, the second voltage level being higher than the first voltage level, wherein the memory device fails if the supply voltage is set below the first voltage level when the temperature of the memory device is below the temperature threshold, and wherein the second voltage level is a memory device manufacturer specified minimum level of the supply voltage required to operate the memory device correctly for all memory states; and

in response to determining the temperature of the memory device is above the temperature threshold, maintain the supply voltage of the memory device.

11. The system of claim 10, wherein the inactive state comprises a self refresh mode of the memory device.

12. The system of claim 10, wherein the processor logic circuitry and/or stored program code is further to:

communicate with the voltage regulator to disable a termination voltage of the memory device.

13. The system of claim 10, wherein the processor logic circuitry and/or stored program code is further to:

change an on-die termination of one or more signals of the processor logic that are coupled with the memory device.

14. The system of claim 10, wherein the memory device comprises Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) device.