Spin orbit torque (SOT) magnetic memory cell and array

• US 9,830,968 B2
• Filed: 09/15/2016
• Issued: 11/28/2017
• Est. Priority Date: 03/16/2016
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shimomura, Naoharu, Asao, Yoshiaki, Ishihara, Takamitsu
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): CHO, SUNG IL
• Application Number:
  US15/266,120
• Publication Number:
  US 20170270985A1
• Time in Patent Office: 439 Days
• Field of Search: 365158, 365173, 365175, 257421, 257295
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/18 using Hall-effect devices
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A magnetic memory according to an embodiment includes: at least one memory cell, the memory cell comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including an anode and a cathode, one of the anode and the cathode being electrically connected to the first magnetic layer; and a transistor including third and fourth terminals and a control terminal, the third terminal being electrically connected to the first terminal.

Claims

1. A magnetic memory comprising:

a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal;

a magnetoresistive element including;

a first magnetic layer having a fixed magnetization;

a second magnetic layer having a changeable magnetization and being disposed between the portion and the first magnetic layer; and

a nonmagnetic layer between the first magnetic layer and the second magnetic layer;

a diode including a third terminal and a fourth terminal, the third terminal being electrically connected to the first magnetic layer;

a transistor including fifth and sixth terminals and a control terminal, the fifth terminal being electrically connected to the first terminal; and

a circuit electrically connected to the second terminal, the fourth terminal, the sixth terminal, and the control terminal,

wherein

when information is to be written into the second magnetic layer, the circuit switches on the transistor, applies a reverse bias to the diode, and supplies current between the second terminal and the sixth terminal, and

when information is to be read from the second magnetic layer, the circuit switches off the transistor, and supplies current between the second terminal and the fourth terminal.

2. The memory according to claim 1, further comprising:

a first wiring electrically connected to the second terminal, and a second wiring electrically connected to the fourth terminal,

wherein a direction from a source toward a drain of the transistor intersects with respective directions in which the first wiring and the second wiring extend.

3. The memory according to claim 1, wherein the diode is a schottky diode or an MIM diode, the MIM diode having two electrodes with different work functions.

4. The memory according to claim 1, wherein the diode is a schottky diode having an uneven impurity concentration.

5. The magnetic memory according to claim 1, wherein the transistor is a recessed transistor.

6. The magnetic memory according to claim 1, further comprising:

a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal,

wherein the first and third wirings extend in a first direction, and the second and fourth wirings extend in a second direction.

7. The magnetic memory according to claim 1, further comprising:

a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal,

wherein a direction in which the first wiring extends intersects with respective directions in which the second and fourth wirings extend, and a direction in which the third wiring intersects with respective directions in which the second and fourth wirings extend.

8. The magnetic memory according to claim 1, wherein the circuit includes a first circuit electrically connected to the fourth terminal and the control terminal, and a second circuit electrically connected to the second terminal and the sixth terminal.

9. A magnetic memory comprising:

a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal;

a magnetoresistive element including;

a first magnetic layer having a fixed magnetization;

a second magnetic layer having a changeable magnetization and being disposed between the portion and the first magnetic layer; and

a nonmagnetic layer between the first magnetic layer and the second magnetic layer;

a bidirectional diode including a third terminal and a fourth terminal, the third terminal being electrically connected to the first magnetic layer;

a transistor including fifth and sixth terminals and a control terminal, the fifth terminal being electrically connected to the first terminal; and

a circuit electrically connected to the second terminal, the fourth terminal, the sixth terminal, and the control terminal,

wherein

when information is to be written into the second magnetic layer, the circuit switches on the transistor, applies a voltage equal to or less than a threshold value to the bidirectional diode, and supplies current between the second terminal and the sixth terminal, and

when information is to be read from the second magnetic layer, the circuit switches off the transistor, and supplies current between the second terminal and the fourth terminal.

10. The memory according to claim 9, further comprising:

a first wiring electrically connected to the second terminal and a second wiring electrically connected to the fourth terminal, wherein a direction from a source toward a drain of the transistor intersects with respective directions in which the first wiring and the second wiring extend.

11. The magnetic memory according to claim 9, wherein the transistor is a recessed transistor.

12. The magnetic memory according to claim 9, further comprising:

a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal,

wherein the first and third wirings extend in a first direction, and the second and fourth wirings extend in a second direction.

13. The magnetic memory according to claim 9, further comprising:

a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal, wherein a direction in which the first wiring extends intersects with respective directions in which the second and fourth wirings extend, and a direction in which the third wiring intersects with respective directions in which the second and fourth wirings extend.

14. The magnetic memory according to claim 9, wherein the circuit includes a first circuit electrically connected to the fourth terminal and the control terminal, and a second circuit electrically connected to the second terminal and the sixth terminal.