Systems and methods for using multiple inductive and capacitive fixtures for applying a variety of plasma conditions to determine a match network model

• US 9,831,071 B2
• Filed: 03/03/2016
• Issued: 11/28/2017
• Est. Priority Date: 05/09/2013
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Howald, Arthur M., Valcore, Jr., John C.
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): Zhang, Haidong
• Application Number:
  US15/059,778
• Publication Number:
  US 20160240356A1
• Time in Patent Office: 635 Days
• CPC Class Codes: G01R 17/00 Measuring arrangements involving comparison with a reference value, e.g. bridge
• CPC Class Codes: G01R 27/04 in circuits having distributed constants , e.g. having very long conductors or involving high frequencies
• CPC Class Codes: H01J 37/32091 the radio frequency energy being capacitively coupled to the plasma
• CPC Class Codes: H01J 37/32183 Matching circuits
• CPC Class Codes: H01J 37/32926 Software, data control or modelling

Abstract

Systems and methods for using multiple inductive and capacitive fixtures for applying a variety of plasma conditions to determine fixed parameters of a match network model are described. The multiple fixtures mimic various plasma conditions without occupying tool time in which a wafer is placed within a plasma chamber to generate the fixed parameters of the match network model.

Claims

1. A method for using multiple fixtures for applying a variety of plasma conditions to determine fixed parameters of a match network model, comprising:

receiving a first output impedance measured at an input of a first fixture;

receiving a first input impedance measured at an input of an impedance matching network, wherein the first input impedance is measured when an output of the impedance matching network is connected to the input of the first fixture;

receiving a second output impedance measured at an input of a second fixture;

receiving a second input impedance measured at the input of the impedance matching network, wherein the second input impedance is measured when the output of the impedance matching network is connected to the input of the second fixture;

applying the first measured output impedance at an output of a match network model to calculate a first predicted input impedance at an input of the match network model when the match network model is assigned a first frequency, a first variable capacitance, a first fixed inductance, a first fixed capacitance, and a first fixed resistance;

applying the second measured output impedance at the output of the match network model to calculate a second predicted input impedance at the input of the match network model when the match network model is assigned a second frequency, a second variable capacitance, the first fixed inductance, the first fixed capacitance, and the first fixed resistance;

determining whether the first predicted input impedance is within a predetermined range from the first measured input impedance and whether the second predicted input impedance is within the predetermined range from the second measured input impedance; and

assigning the first fixed inductance, the first fixed capacitance, and the first fixed resistance to the match network model upon determining that the first predicted input impedance is within the predetermined range from the first measured input impedance and that the second predicted input impedance is within the predetermined range from the second measured input impedance.

2. The method of claim 1,

wherein the first measured input impedance is measured for the first variable capacitance of the impedance matching network when the input of the impedance matching network is connected to an output of a network analyzer operating at the first frequency,

wherein the second measured input impedance is measured for the second variable capacitance of the impedance matching network when the input of the impedance matching network is connected to the output of the network analyzer operating at the second frequency,

the method further comprising:

determining whether the first measured input impedance is within a predetermined threshold of a predetermined impedance;

storing the first frequency and the first variable capacitance upon determining that the first measured input impedance is within the predetermined threshold of the predetermined impedance;

determining whether the second measured input impedance is within the predetermined threshold of the predetermined impedance; and

storing the second frequency and the second variable capacitance upon determining that the second measured input impedance is within the predetermined threshold of the predetermined impedance.

3. The method of claim 1, wherein the first measured input impedance is measured by a network analyzer, wherein the first measured input impedance is a complex value, wherein the input of the impedance matching network is configured to be coupled to a branch circuit of the impedance matching network, wherein the branch circuit is configured to be coupled to an RF generator during processing of a wafer.

4. The method of claim 1, wherein the first measured input impedance is measured for the first variable capacitance of the impedance matching network when the input of the impedance matching network is connected to an output of a network analyzer operating at the first frequency, wherein the first variable capacitance of the impedance matching network is a combined variable capacitance of one or more variable capacitors of the impedance matching network.

5. The method of claim 1, wherein the first fixture is a load impedance fixture for obtaining an S11 measurement and the second fixture is a load impedance fixture for obtaining an S11 measurement.

6. The method of claim 1, wherein the second input impedance is measured by a network analyzer, wherein the second input impedance is a complex value, wherein the input of the impedance matching network is configured to be coupled to a branch circuit of the impedance matching network, wherein the branch circuit is configured to be coupled to an RF generator during processing of a wafer.

7. The method of claim 1, wherein the second measured input impedance is measured for the second variable capacitance of the impedance matching network when the input of the impedance matching network is connected to an output of a network analyzer operating at the second frequency, wherein the second variable capacitance of the impedance matching network is a combined variable capacitance of one or more variable capacitors of the impedance matching network.

8. The method of claim 1, wherein determining whether the first predicted input impedance is within the predetermined range from the first measured input impedance is performed simultaneously with determining whether the second predicted input impedance is within the predetermined range from the second measured input impedance.

9. The method of claim 1, further comprising calculating an output value of a variable at the output of the match network model during a time the match network model is assigned the first fixed inductance, the first fixed capacitance, and the first fixed resistance, wherein calculating the output value of the variable is performed by forward propagating an input value of the variable measured by a sensor connected to an output of an RF generator.

10. A system for using multiple fixtures for applying a variety of plasma conditions to determine fixed parameters of a match network model, comprising:

a processor configured to receive a first output impedance measured at an input of a first fixture,

wherein the processor is configured to receive a first input impedance measured at an input of an impedance matching network, wherein the first measured input impedance is measured when an output of the impedance matching network is connected to the input of the first fixture,

wherein the processor is configured to receive a second output impedance measured at an input of a second fixture,

wherein the processor is configured to receive a second input impedance measured at the input of the impedance matching network, wherein the second measured input impedance is measured when the output of the impedance matching network is connected to the input of the second fixture,

wherein the processor is configured to apply the first measured output impedance at an output of a match network model to calculate a first predicted input impedance at an input of the match network model when the match network model is assigned a first frequency, a first variable capacitance, a first fixed inductance, a first fixed capacitance, and a first fixed resistance,

wherein the processor is configured to apply the second measured output impedance at the output of the match network model to calculate a second predicted input impedance at the input of the match network model when the match network model is assigned a second frequency, a second variable capacitance, the first fixed inductance, the first fixed capacitance, and the first fixed resistance,

wherein the processor is configured to determine whether the first predicted input impedance is within a predetermined range from the first measured input impedance and whether the second predicted input impedance is within the predetermined range from the second measured input impedance,

wherein the processor is configured to assign the first fixed inductance, the first fixed capacitance, and the first fixed resistance to the match network model upon determining that the first predicted input impedance is within the predetermined range from the first measured input impedance and that the second predicted input impedance is within the predetermined range from the second measured input impedance; and

a memory device coupled to the processor.

11. The system of claim 10,

wherein the first measured input impedance is measured for the first variable capacitance of the impedance matching network when the input of the impedance matching network is connected to an output of a network analyzer operating at the first frequency,

wherein the processor is configured to determine whether the first measured input impedance is within a predetermined threshold of a predetermined impedance,

wherein the processor is configured to store within the memory device the first frequency and the first variable capacitance upon determining that the first measured input impedance is within the predetermined threshold of the predetermined impedance,

wherein the second measured input impedance is measured for the second variable capacitance of the impedance matching network when the input of the impedance matching network is connected to the output of the network analyzer operating at the second frequency,

wherein the processor is configured to determine whether the second measured input impedance is within the predetermined threshold of the predetermined impedance, and

wherein the processor is configured to store the second frequency and the second variable capacitance in the memory device upon determining that the second measured input impedance is within the predetermined threshold of the predetermined impedance.

12. The system of claim 10, wherein the first measured input impedance is measured by a network analyzer, wherein the first measured input impedance is a complex value, wherein the input of the impedance matching network is configured to be coupled to a branch circuit of the impedance matching network, wherein the branch circuit is configured to be coupled to an RF generator during processing of a wafer.

13. The system of claim 10,

wherein the first measured input impedance is measured for the first variable capacitance of the impedance matching network when the input of the impedance matching network is connected to an output of a network analyzer operating at the first frequency,

wherein the first variable capacitance of the impedance matching network is a combined variable capacitance of one or more variable capacitors of the impedance matching network,

wherein the second measured input impedance is measured for the second variable capacitance of the impedance matching network when the input of the impedance matching network is connected to the output of the network analyzer operating at the second frequency,

wherein the second variable capacitance of the impedance matching network is a combined variable capacitance of the one or more variable capacitors of the impedance matching network.

14. A system for using multiple fixtures for applying a variety of plasma conditions to determine fixed parameters of a match network model, comprising:

an impedance matching network having an input and an output;

a first fixture;

a network analyzer,

wherein the impedance matching network is not connected to a radio frequency (RF) generator,

wherein the network analyzer is configured to measure a first output impedance at an input of the first fixture when the first fixture is connected to the network analyzer,

wherein the network analyzer is further configured to measure a first input impedance at an input of the network analyzer when the network analyzer is connected to the impedance matching network and the impedance matching network is connected to the first fixture;

a processor connected to the network analyzer,

wherein the processor is configured to receive the first measured output impedance and the first measured input impedance from the network analyzer,

a second fixture,

wherein the network analyzer is configured to measure a second output impedance at an input of the second fixture when the network analyzer is connected to the second fixture,

wherein the network analyzer is further configured to measure a second input impedance at the input of the network analyzer when the second fixture is connected to the impedance matching network and the network analyzer is connected to the impedance matching network,

wherein the processor is configured to receive the second measured output impedance and the second measured input impedance from the network analyzer,

wherein the processor is configured to apply the first measured output impedance at an output of a match network model to calculate a first predicted input impedance at an input of the match network model when the match network model is assigned a first frequency, a first variable capacitance, a first fixed inductance, a first fixed capacitance, and a first fixed resistance,

wherein the processor is configured to apply the second measured output impedance at the output of the match network model to calculate a second predicted input impedance at the input of the match network model when the match network model is assigned a second frequency, a second variable capacitance, the first fixed inductance, the first fixed capacitance, and the first fixed resistance,

wherein the processor is configured to determine whether the first predicted input impedance is within a predetermined range from the first measured input impedance and whether the second predicted input impedance is within the predetermined range from the second measured input impedance,

wherein the processor is configured to assign the first fixed inductance, the first fixed capacitance, and the first fixed resistance to the match network model upon determining that the first predicted input impedance is within the predetermined range from the first measured input impedance and that the second predicted input impedance is within the predetermined range from the second measured input impedance.

15. The system of claim 14,

wherein the first measured input impedance is measured for the first variable capacitance of the impedance matching network when the input of the impedance matching network is connected to an output of the network analyzer operating at the first frequency,

wherein the processor is configured to determine whether the first measured input impedance is within a predetermined threshold of a predetermined impedance;

wherein the processor is configured to store the first frequency and the first variable capacitance in a memory device upon determining that the first measured input impedance is within the predetermined threshold of the predetermined impedance,

wherein the second measured input impedance is measured for the second variable capacitance of the impedance matching network when the input of the impedance matching network is connected to the output of the network analyzer operating at the second frequency,

wherein the processor is configured to determine whether the second measured input impedance is within the predetermined threshold of the predetermined impedance,

wherein the processor is configured to store the second frequency and the second variable capacitance in the memory device upon determining that the second measured input impedance is within the predetermined threshold of the predetermined impedance.

16. The system of claim 14, wherein the first measured input impedance is a complex value, wherein the input of the impedance matching network is configured to be coupled to a branch circuit of the impedance matching network, wherein the branch circuit is configured to be coupled to the RF generator during processing of a wafer.

17. The system of claim 14,

wherein the first measured input impedance is measured for the first variable capacitance of the impedance matching network when the input of the impedance matching network is connected to an output of the network analyzer operating at the first frequency,

wherein the first variable capacitance of the impedance matching network is a combined variable capacitance of one or more variable capacitors of the impedance matching network.

18. The system of claim 14,

wherein the network analyzer is configured to measure the first input impedance when the network analyzer is operated at the first frequency and the impedance matching network has the first variable capacitance,

wherein the network analyzer is configured to measure the second input impedance when the network analyzer is operated at the second frequency and the impedance matching network has the second variable capacitance.