Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
First Claim
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1. An integrated circuit (IC), comprising at least:
- a standard cell area that includes a mix of logic cells and fill cells of different widths and uniform heights;
wherein said integrated circuit includes at least a first Design of Experiments (DOE), said first DOE comprising at least two GATE snake-open-configured, non-contact electrical measurement (NCEM)-enabled fill cells, wherein each GATE snake-open-configured, NCEM-enabled fill cell comprises at least;
first and second elongated conductive supply rails, formed in at least one metal layer, extending horizontally across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of the standard cell region;
a NCEM pad, formed in at least one conductive layer;
a rectangular test area, defined by a first gate contact (GATECNT) feature and a second GATECNT feature;
wherein the test area further comprises;
at least first and second elongated GATE features, said first and second GATE features arranged in parallel and extending longitudinally in a vertical direction; and
,at least first and second elongated GATECNT features, arranged in parallel and extending longitudinally in the horizontal direction,wherein the GATECNT features are positioned to intersect the GATE features to form a conductive snake, having a length defined by the longitudinal extents of the GATECNT and GATE features that form the snake;
a first conductive pathway that electrically connects the first GATECNT feature to said pad; and
,a second conductive pathway that electrically connects the second GATECNT feature to a permanently or virtually grounded structure;
wherein each of the GATE snake-open-configured, NCEM-enabled fill cell in the first DOE is configured to present an open circuit or excessive resistance in its GATE features as abnormally low pad-to-ground conductance or abnormally high pad-to-ground resistance, detectable by voltage contrast inspection of the pad; and
,wherein the GATE snake-open-configured, NCEM-enabled fill cells of the first DOE differ at least in terms of the lengths of their respective snakes.
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Abstract
Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, including GATE-snake-open and/or GATE-snake-resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode.
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Citations
20 Claims
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1. An integrated circuit (IC), comprising at least:
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a standard cell area that includes a mix of logic cells and fill cells of different widths and uniform heights; wherein said integrated circuit includes at least a first Design of Experiments (DOE), said first DOE comprising at least two GATE snake-open-configured, non-contact electrical measurement (NCEM)-enabled fill cells, wherein each GATE snake-open-configured, NCEM-enabled fill cell comprises at least; first and second elongated conductive supply rails, formed in at least one metal layer, extending horizontally across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of the standard cell region; a NCEM pad, formed in at least one conductive layer; a rectangular test area, defined by a first gate contact (GATECNT) feature and a second GATECNT feature; wherein the test area further comprises; at least first and second elongated GATE features, said first and second GATE features arranged in parallel and extending longitudinally in a vertical direction; and
,at least first and second elongated GATECNT features, arranged in parallel and extending longitudinally in the horizontal direction, wherein the GATECNT features are positioned to intersect the GATE features to form a conductive snake, having a length defined by the longitudinal extents of the GATECNT and GATE features that form the snake; a first conductive pathway that electrically connects the first GATECNT feature to said pad; and
,a second conductive pathway that electrically connects the second GATECNT feature to a permanently or virtually grounded structure; wherein each of the GATE snake-open-configured, NCEM-enabled fill cell in the first DOE is configured to present an open circuit or excessive resistance in its GATE features as abnormally low pad-to-ground conductance or abnormally high pad-to-ground resistance, detectable by voltage contrast inspection of the pad; and
,wherein the GATE snake-open-configured, NCEM-enabled fill cells of the first DOE differ at least in terms of the lengths of their respective snakes. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit (IC), comprising at least:
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a standard cell area that includes a mix of logic cells and fill cells of different widths and uniform heights; wherein said integrated circuit includes at least a first DOE, said first DOE comprising at least two GATE snake-open-configured, NCEM-enabled fill cells, wherein each GATE snake-open-configured, NCEM-enabled fill cell comprises at least; first and second elongated conductive supply rails, formed in at least one metal layer, extending horizontally across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of the standard cell region; a NCEM pad, formed in at least one conductive layer; a rectangular test area defined by a first GATECNT feature and a second GATECNT feature; wherein, the test area further comprises; at least first and second elongated GATE features, said first and second GATE features arranged in parallel and extending longitudinally in a vertical direction; and
,at least first and second elongated GATECNT features, said first and second GATECNT features arranged in parallel and extending longitudinally in the horizontal direction, wherein the GATECNT features are positioned to intersect the GATE features to form a conductive snake, having a length defined by the longitudinal extents of the GATECNT and GATE features that form the snake; a first conductive pathway that electrically connects the first GATECNT feature to said pad; and
,a second conductive pathway that electrically connects the second GATECNT feature to a permanently or virtually grounded structure; wherein each of the GATE snake-open-configured, NCEM-enabled fill cells in the first DOE is configured to present an open circuit or excessive resistance in its GATE features as abnormally low pad-to-ground conductance or abnormally high pad-to-ground resistance, detectable by voltage contrast inspection of the pad; and
,wherein the first and second GATE snake-open-configured, NCEM-enabled fill cells of the first DOE differ at least in terms of a presence or absence, within the test area, of mask-patterned feature(s) in layers that lie immediately above the GATECNT layer or immediately below the GATE layer. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An integrated circuit (IC), comprising at least:
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a standard cell area that includes a mix of logic cells and fill cells of different widths and uniform heights; wherein said integrated circuit includes at least a first DOE, said first DOE comprising at least two GATE snake-open-configured, NCEM-enabled fill cells, wherein each GATE snake-open-configured, NCEM-enabled fill cell comprises at least; first and second elongated conductive supply rails, formed in at least one metal layer, extending horizontally across the entire width of said cell, and configured for compatibility with corresponding supply rails contained in the logic cells of the standard cell region; a NCEM pad, comprised of; at least two parallel, elongated AACNT features, extending longitudinally in a first direction; and
,at least two parallel, elongated GATECNT features, extending longitudinally in a second direction, perpendicular to the first direction; wherein each of the AANCT features intersects each of the GATECNT features; a rectangular test area, defined by a first GATECNT feature and a second GATECNT feature; wherein the test area further comprises; at least first and second GATE features, said first and second GATE features arranged in parallel and extending longitudinally in a vertical direction; and
,at least first and second GATECNT features, arranged in parallel and extending longitudinally in the horizontal direction; wherein the GATECNT features are positioned to intersect the GATE features to form a conductive snake, having a length defined by the longitudinal extents of the GATECNT and GATE features that form the snake; a first conductive pathway that electrically connects the first GATECNT feature to said pad; and
,a second conductive pathway that electrically connects the second GATECNT feature to a permanently or virtually grounded structure; and wherein each of the GATE snake-open-configured, NCEM-enabled fill cells in the first DOE is configured to present an open circuit or excessive resistance defects in its GATE features as abnormally low pad-to-ground conductance or abnormally high pad-to-ground resistance, detectable by voltage contrast inspection of the pad. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification
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InventorsLam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, De, Indranil, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Haigh, Jonathan, Hess, Christopher, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu
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Primary Examiner(s)Le, Son
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Application NumberUS15/188,027Time in Patent Office525 DaysField of SearchUS Class CurrentCPC Class CodesG01R 31/2884 using dedicated test connec...G06F 11/079 Root cause analysis, i.e. e...G06F 30/30 Circuit designG06F 30/39 Circuit design at the physi...G06F 30/392 Floor-planning or layout, e...G06F 30/398 Design verification or opti...H01L 2027/11866 Gate electrode terminals or...H01L 2027/11875 Wiring region, routingH01L 2027/11885 Two levels of metalH01L 2027/11887 Three levels of metalH01L 22/20 Sequence of activities cons...H01L 22/26 Acting in response to an on...H01L 22/34 Circuits for electrically c...H01L 23/5226 Via connections in a multil...H01L 23/528 Geometry or layout of the i...H01L 27/0207 Geometrical layout of the c...H01L 27/11803 using field effect technologyH01L 27/11807 CMOS gate arraysH01L 29/0649 Dielectric regions, e.g. Si...H01L 29/0684 characterised by the shape,...View All
