Semiconductor package with embedded output inductor

• US 9,831,159 B2
• Filed: 04/19/2016
• Issued: 11/28/2017
• Est. Priority Date: 06/09/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Cho, Eung San, Galipeau, Darryl, Clavette, Danny
• Primary Examiner(s): LUKE, DANIEL M
• Application Number:
  US15/132,943
• Publication Number:
  US 20160365304A1
• Time in Patent Office: 588 Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 2224/8484 Sintering
• CPC Class Codes: H01L 2224/8485 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/495 Lead-frames or other flat leads H01L23/498 takes precedence; lead frame interconnections between components H01L23/52
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49537 Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 29/16 : including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first patterned conductive carrier, as well as a magnetic material situated over leads of the first patterned conductive carrier. The semiconductor package also includes a second patterned conductive carrier attached over the first patterned conductive carrier, the control and sync transistors, and the magnetic material. Leads of the second patterned conductive carrier overlie the magnetic material and are coupled to the leads of the first patterned conductive carrier so as to form windings of an output inductor for the power converter switching stage, the output inductor being integrated into the semiconductor package.

Claims

1. A semiconductor package comprising:

a driver IC (Integrated Circuit), a control transistor, and a sync transistor of a power converter, wherein said driver IC and said control and sync transistors are attached over a first patterned conductive carrier and said driver IC is configured to drive said control and sync transistors to develop a voltage at a switch node of said power converter;

a magnetic material situated over a plurality of leads of said first patterned conductive carrier;

a second patterned conductive carrier that is not attached over said driver IC and is attached over said plurality of leads of said first patterned conductive carrier, said control and sync transistors, and said magnetic material;

wherein a plurality of leads of said second patterned conductive carrier overlie said magnetic material and said control and sync transistors and are coupled to said plurality of leads of said first patterned conductive carrier so as to form said switch node of said power converter and windings of an output inductor for said power converter, said output inductor being integrated into said semiconductor package.

2. The semiconductor package of claim 1, wherein said magnetic material comprises a magnetic core.

3. The semiconductor package of claim 1, wherein said magnetic material comprises a molding compound impregnated with magnetic particles.

4. The semiconductor package of claim 1, wherein a drain of said control transistor is attached to a control drain segment of said first patterned conductive carrier.

5. The semiconductor package of claim 1, wherein a source of said sync transistor is attached to a sync source segment of said first patterned conductive carrier.

6. The semiconductor package of claim 1, wherein said second patterned conductive carrier couples a source of said control transistor to a drain of said sync transistor to provide said switch node of said power converter.

7. The semiconductor package of claim 1, wherein said control and sync transistors comprise silicon transistors.

8. The semiconductor package of claim 1, wherein said control and sync transistors comprise group III-V transistors.

9. The semiconductor package of claim 1, wherein said first patterned conductive carrier comprises a portion of a lead frame.

10. The semiconductor package of claim 1, wherein said second patterned conductive carrier comprises a portion of a lead frame.

11. A method for fabricating a semiconductor package, said method comprising:

attaching a driver IC (Integrated Circuit), a control transistor and a sync transistor of a power converter over a first patterned conductive carrier, wherein said driver IC is configured to drive said control and sync transistors to develop a voltage at a switch node of said power converter;

situating a magnetic material over a plurality of leads of said first patterned conductive carrier;

attaching a second patterned conductive carrier over said plurality of leads of first patterned conductive carrier, said control and sync transistors, and said magnetic material and not over said driver IC;

wherein a plurality of leads of said second patterned conductive carrier overlie said magnetic material and said control and sync transistors and are coupled to said plurality of leads of said first patterned conductive carrier so as to form said switch node of said power converter and windings of an output inductor for said power converter, said output inductor being integrated into said semiconductor package.

12. The method of claim 11, wherein said magnetic material comprises a magnetic core.

13. The method of claim 11, wherein said magnetic material comprises a molding compound impregnated with magnetic particles.

14. The method of claim 11, wherein a drain of said control transistor is attached to a control drain segment of said first patterned conductive carrier.

15. The method of claim 11, wherein a source of said sync transistor is attached to a sync source segment of said first patterned conductive carrier.

16. The method of claim 11, wherein said second patterned conductive carrier couples a source of said control transistor to a drain of said sync transistor to provide said switch node of said power converter.

17. The method of claim 11, wherein said control and sync transistors comprise silicon transistors.

18. The method of claim 11, wherein said control and sync transistors comprise group III-V transistors.